There are many uses for a good current source, in particular, to drive a noise generator, Noise Source TWS-N15. Not much to write home about, but because of frequent requests, I am publishing the circuit here. It will work for small current from 2 or 3 mA up to 10 or 20 mA with no problem, and very little drift over temperature and time. For R, uses a good resistor. Input voltage can be up to 35 V, or even higher.
This blog is hosted by a professional provider, but the manuals archive (which needs quite a bit of storage), and other webpages, and my fileserver, is running on two machines, a Dell OptiPlex FX160 as the main, eco-efficient system (in Germany), and a Dell PowerEdge SC1425 with a Raid 1, 3 TB hard drive system as the backup, and currently my main system in Japan (where I am living on a temporary business assignment). Recently, the SC1425 failed, it just would not start up anymore. Power supply seems OK – likely, a severe issue. Checked all the memory and everything, but to no avail.
After fiddling around for about 2 hours, and still no success, I decided to order a new server – a new old server, Dell PowerEdge 850. Just about 35 Dollars used. Rather than 2x XEON processors, it has a Pentium D, 3.2 GHz Dual-Core. Plenty of power for a web- and fileserver.
A couple of days later, the unit arrived – removed the SATA Raid controller (running on Ubuntu with software Raid), and some BIOS settings (activate SATA, disable Keyboard error, enable boot from USB, default power up status is ON) plus BIOS Update. Also, reconfigured the router to make sure this machine will get all the HTTP requests.
A few tests – the harddrive is working fine, about 100 MB/s (sure there is a cache). The Raid 1 is up with no repairs or anything.
A quick check – also the web server is reachable.
I wouldn’t recommend a single PowerEdge for your super critical applications, but they are pretty good for the current cost, as long as you don’t mind the fan noise.
There are many circuits around in the web, related to GPSDOs, and a more sophisticated design with a self-steering u-blox receiver has been published earlier here. Now I felt tempted to try an easier approach, without the hassle of precision references, operational amplifiers, DAC, and other devices that are great but high cost when you need to avoid noise and other complications.
Essentially, this design is a clean-up PLL, with some monitoring of the receiver, and the PLL health. All monitored by a simple 8 bit microcontroller, an ATMega8-16PU in this case.
We have some elements here, (1) the OCXO and amplifier, distribution amplifier – to provide the outputs, 4 in this case, and a good TTL level 10 MHz signal for the PLL, (2) a u-blox receiver, configured to provide either 5 Hz flashing in non-locked condition (no GPS reception, or no good reception), and 125 kHz, 50% duty cycle as a phase reference in locked condition, (3) the MCU, ATMega8, that is configuring the GPS received, providing a 125 kHz signal derived from the 10 MHz OCXO (the OCXO is used as the microprocessor clock – don’t introduce a new clock in such circuits, which will only lead to spurious signals!), (4) a 74HC86 that is used as a phase detector, and to convert the GPS output (a 3.3 V signal) to 5 V level.
That’s the OCXO and distribution amplifier…
The phase detector…
The controller and PLL filter – a simple two pole filter. It replaces all the expensive references, DACs and opamps of the more sophisticated designs. There is another small, faster filter to convert the phase angle to a voltage – converted by the 10 bit ADC of the ATMega8, 1 bit is about 4 ns.
The circuit full view…
Some first tests turned out well. Monitoring the OCXO phase with a scope…
To do a more thorough tests, without all my various test gear that it back in good old Germany, I used the 10 MHz to run another GPS receiver (after upconverting to a 26 MHz clock), then the NAV-CLOCK message can be used to report phase and drift. The short term stability of the OCXO is better than the GPS, as can be seen, but there is no long term drift – because the OCXO is now steered by the 1st GPS receiver via the PLL (XOR phase detector and loop filter).
The phase detection is done at 125 kHz, a convenient frequency for precise measurement, and high enough for filtering.
About 20 ns of jitter are clearly visible in the u-blox output, because it is running on a 48 MHz internal clock.
The circuit is running well, because of the few parts the cost is low and should be easy to reproduce. Let me know in case you need the ATMega code (written in GCC).
The display shows the phase angle, essentially, the duty cycle of the phase comparator output, the stability of the OCXO voltage (by a low pass algorithm), and the lock condition of the GPS (detected by measuring the frequency with timer0 of the ATMega8, and the INT0 interrupt at rising flank to reset the timer).
Phase noise is very small, there are no visible spurs (the lines seen on the screen relate to recalibration events of the analyzer rather than spurious signals, except those at +-125 kHz – at -90 dBc – probably you can get rid of these by better shielding and compartmentalization).
Sure there could be more sophisticated phase noise measurement, by analyzing the control voltage with a low frequency analyzer. I may proceed with such analysis these days but don’t expect to find much, anyway, would be best to fit the circuit to a shielded box first.
All in all, I believe this is a very workable solution that will give you great performance at lowest cost, and with little effort. Sure it will work with various types of OCXOs, the Trimble unit used is generally very good in terms of drift and phase noise. Be aware that some newer Trimble units aren’t all that good. The OCXO draws about 2 Amps at 12 Volts upon startup, but it is OK to start it with a current limited supply, at about 1 Amp, if you don’t want to overdesign the power supply.
Many attempts have been made in the past to provide a low phase noise 10 MHz signal as a frequency reference, however recently I experienced some trouble because of ground loops. Normally no problem to decouple from DC voltages, but still the ground stays connected. The only way to avoid such ground loops is to use potential-free isolation, best using transformers. Capacitive coupling may be an option, but it is best avoided, at least it is though to get good isolation, say 2 kV or above, with capacitors that can transmit 10 MHz, at reasonable cost and size.
I am looking for about 1 V p-p, reasonably square shape output, into 50 Ohms, or TTL level (about 5 V) into high impedance. About 5-10 dBm at the 1st harmonic, 10 MHz. So we need to drive about 15 mA through a 50 Ohm load.
As amplifier elements, I am using 74HCU04 unbuffered inverters, these are balanced for propagation delay, and I have plenty of these in a box. The HCU04 is essentially a single stage inverter, a gate with a pretty good linear region – an amplifier. Propagation delay is about 5 ns at room temperature, so it is good solution to amplify clocks, and so on. We are using it to amplify a 10 MHz signal from an OCXO.
For isolation, looking for some small transformers (generally speaking ethernet transformers will work well), I found the PE-65612NL at low cost (list price is about 4 USD per piece, but some sellers have them at a small fraction of this cost, most likely, from surplus). These are 1:1, 2 kV min, signal transformers originally intended for digital audio signal separation. Good enough for our purposes.
A really affordable offer… sure you can substitute any other reasonable signal transformer that can cope with at least 20 mW, and is reasonably inexpensive.
The schematic – first, a single HCU04 is used to square up the OCXO output, and then distribute to 3 outputs, two are used to drive 2 isolated outputs each (4 outputs total), the other output is routed to a PLL circuit (because this isolation amp is part of a GPSDO). Any phase drift of the 1st stage HCU04 introduced by thermal and other slow effects will be canceled to some part by the GPS loop (because the sampling of the phase is very close to the isolated outputs, only followed by a set of paralleled-up gates) – although I don’t expect such drift.
The resistors were selected as 3×330 Ohm, giving about 100 Ohms source resistance and about 1.4 V pp when terminated in 50 Ohms.
Output power is fairly consistent, like, +-0.2 dBm when comparing 4 units. Fundamental output at 8 dBm is exactly the right range. Probably you can adjust it in the range of 5 to 10 nominal without changing much the other characteristics of the circuit, by changing the resistor values from the paralleled-up gates to the isolation transformer.
In reply to an earlier post, GPSDO Update, I received the following great implementation of a GPSDO using u-blox receivers. The pictures are rather self explanatory.
Hello again Simon!
I trust you are well and are enjoying the year end break.
We ( My good Wife and I..) have put your GPSDO software to good use. We used your message processing code almost as is, and added the various functions to drive my specific hardware and DAC, etc.
I have built up the complete GPSDO, with the 1-50MHz Analogue Devices AD9854 Quadrature DDS as a signal generator, provided with a 200MHz clock from the SI5351 PLL.
I also have a ‘signal generator’ output from another Si5351 channel, 1 to 200MHz, and a third channel output. square wave, from the GPS time pulse output, and can set outputs from 1Hz to 10MHz in decade steps.
I used a 7inch NEXTION graphics display for the display and control inputs ( touch screen) – that works very nicely!
I have run the unit for a few days now, and logged a 48hour period of data, every 10seconds, regarding the clock bias, drift, DAC output voltage etc, and the result looks very good indeed.
I am very pleased with the instrument and grateful for your assistance in providing your code. Thank You!
I have attached a few photos for interest.
Kind regards, and have a very good Christmas!
Joe and Gisela.
Coming back to an earlier post, Noise source design, I wanted to post the final results, and the looks of these noise sources.
The case is an aluminum extrusion design, and the lids are milled to accomodate the BNC and SMA connectors. The SMA is a really high quality connector. No point in using a noise source with a cheap connector – you are normally going to connect and disconnect this often.
The constant current supply is optimized for the maximum noise output, normally, about 8 mA. The design is a current mirror, with a TL431 precision reference.
The noise section is soldered with 0603 SMD mostly, on a FR4 board.
Foam and copper tape to avoid any foreign signals getting into it. Spurious signals can mean big trouble with noise measurements.
Return loss, I think it is pretty good.
After some optimization of the circuit, the ENR output is now pretty flat, even with no specially expensive noise diode.
After all, pretty happy with the device, and others are happy two, as I give them away at low cost. If you need one, let me know.
For year I have been using various Molex style connectors, 2.5 mm, 3.96 mm, and so on, but never by crimping own contacts. Criming is a special art, and if not done properly, it can cause all kinds of reliability issues. So I usually purchased pre-crimped wires, and just assembled them for contact blocks. In other cases, I just used regular pliers to mount wires to contacts, and soldered them in (best, to pre-tin the wire, then mount it in the contact with small pliers, then solder it in – this will result in a very reliable connection. Also, never use low quality wire, only full copper core, heavily tinned wire, UL 1007 or similar.
But why not try to crimp contacts ourselves and add a new capability to the workshop? So I went ahead, and ordered a low cost pair of crimping pliers, EUR 12, not bad.
It made it from China to Japan very quickly, delivered by a friendly postman (here they are very friendly). That’s the tool: quality looks quite OK, and the steel is pretty hard. Sure this is not a high throughput production tool – I am looking at a few 10s of contacts every year, not 1000s.
Step 1, remove the insulation from the wire, and get the contact and pliers ready.
Step 2, insert the contact in the pliers, and close it until flush (don’t apply much force).
Step 3, insert the wire, and crimp the inner connection. Don’t get any of the insulation caught up by the crimp. It is a bit inconvenient to get the contact out of the pliers, probably will make a special tool for it (a U-shape bent piece of steel sheet metal to push out the contact).
Step 4, Inspect the inner crimp. Use a magnifier if necessary (make sure no plastic and insulation got into the crimp area). Pull on the wire, it must be firmly held (a properly crimped wire can’t be pulled out by any reasonable force).
Step 5, slightly close the insulation crimp using the tip of the pliers.
Step 6, establish the insulation crimp.
Step 7 – It’s ready. Inspect. Carry out pulling test.
Looking for the CRT front bezel and frame to fix another unit, I found this 8412A Phase Magnitude Display on a Japanese auction site for EUR 8 plus shipping, really affordable! Also, I believe it to be a great source of spare parts, because there are many of the HP standard semiconductors of the 70s inside.
The unit arrived in great shape, almost too good to take it apart – maybe we can use it for something cool, like a CRT clock or some soundwave visualization unit?
How to get it to work – checked the 8412A manual, and, unfortunately, it needs a whole lot of unusual supply voltages (the 8412A slides into the 8410A/B Network Analyzer mainframe) – not easy to operate it without the mainframe. 175 Volts AC, to drive the CRT and 6.3 VAC heater, and +-20 VDC, for the other circuits.
Some pictures of the unit…
The dangers of high voltage are fairly obvious!!
Quite similar to other HP units – amazing how often they recycled the design!
2.000 kOhm, +- 0.05% resistors, a matched pair – not bad! Definitely, a lot of good parts in this unit, including high voltage parts, a good CRT, many semiconductors and transistor pairs, mica capacitors, etc.
HP even supplied a small test board to make service and adjustment easier! Great!!
With the Si5351A mastered, time for some tests with the actual application, the GPS receiver (and later GPSDO system).
Two tests were performed:
(1) Using the Si5351A clock generator with a standard, not specifically selected or particularly stable crystal. Presumably, an AT cut crystal, running at 25 MHz.
(2) With the Si5351A driven by a OCXO (HP 10811A, part of a 8662A unit – will be later replaced by a stand-alone unit using a HP 10811A with power supply and distribution amplifier, but essentially, to the same effect).
The first test, we need to set the registers of the Si5351A (check the Silicon Labs AN 618 Application Note – check it in a quiet hour, because it has a lot of heavy content…). 25 MHz clock input, 26 MHz OSC0 output – can be achieved by running the VCO at 650 MHz, and integer-only dividers.
For the calculation, I use a self-made Excel sheet, which allows me to play around with the numbers to figure out the best combination of dividers and VCO frequency.
Here, the over test setup:
That’s the Xtal used – it came with the board, and I couldn’t find any data on it. Appears to be an AT cut crystal. Starting from room temperature, frequency, will go down with increasing temperature, and up with colder temperatures.
Such temperature variation is easily introduced here in Japan. First, keeping the room at 22 degC by the aircon (A/C) unit, then switching it off overnight (cooling the room by a few degrees, maybe down to 17 degC), then, next morning, heating up again to 22 degC (and a bit more as we had a sunny day).
The detail below also shows the small thermal mass of the Si5351A, free-hanging in air. Better to enclose it or to add some thermal mass later, to avoid thermal-gradient introduced noise or instability. You can clearly see the on-off cycles of the A/C unit regulating the room temperature.
After all this study, we find out that we can use the GPS and Xtal as a quarz thermometer (such thermometers really exist!)!
Test 2, now running with a 10 MHz reference clock, and still 26 MHz output to the u-blox M7 (in all cases, the u-Blox has been modified by removing the TCXO, and feeding the clock signal directly to the GPS chip). Sure I known that I am running the Si5351A outside of the specified range – but after all the research, Si5351A Spec, Myth and Truth, I believe this is OK.
The test setup – note the dotted additions – this will be the later phase locked circuit.
The register settings – running the Si5351A VCO at 780 MHz allows the use of integer-only dividers.
Capacitance set to 4 pF (the lowest value possible for the Si5351A, but it has little effect on sensitivity, 10 pF default setting works as well, maybe 1 dB decreased sensitivity, but we are anyway feeding more then enough power to the Xtal A input of the Si5351A).
The GPS clock drift data – not very exiting – no drift at all, less than 1 ppb over a few hours. There is a slight frequency offset, because the electronic frequency control (EFC) of the 10811A OCXO set to 0 Volt, rather to the proper value for exactly 10 MHz, only for convenience and to avoid any artifacts from EFC DAC noise or drift.
The position accuracy also seems better with the stable oscillator, but may need to check this again after acquiring data for a full day or so.
All in all, more than a proof of concept. Next steps include setting up a stand-alone OCXO (I have a couple of spare 10811A OCXOs around), a distribution amplifier (nothing special, planning to use some 74HC14 with small signal transformers for isolation), and getting the PLL code into a microcontroller. For the DAC, I will use a fairly basic model, and provide a low pass filter at the output (much faster than the digitally-generated long time constant low pass of the PLL loop, but still slow compared to common standards) to reduce noise.
So far, the bill of material is very low, just a few dollars, including the GPS receiver. My goal is to stay below USD 10 total, excluding the OCXO, to achieve better than 10-9 stability, and an output with no jitter or other issues.
The Si5351 series of silicon-VCOs and clock generators is a quite remarkable achievement of technology. Earlier on, we needed two sets of dividers, PLL control logic, and a VCO – essentially a box full of parts – to realize the same purpose: generating one clock, from another.
While being quite adaptable to all kinds of circumstances and uses, the Si5351A (which is the cheapest, and most common chip – all the others have so many pins, and are in such small package that they are hard to use) has some limitations.
(1) It only has a crystal (XTAL) input, specified over a narrow frequency range. 25 to 27 MHz. Some forum comments suggest that there is a tuned oscillator inside, only working at such frequency, Myth or Truth? For my particular application, I need to drive it by a 10 MHz external clock, because that’s the main frequency source and signal I have available.
(2) The VCO range, 600 to 900 MHz should be selected, according to the instructions. Any chance to use lower frequencies, in case this is needed to get integer-only division ratios? Or higher frequencies? What are the limits?
To test the Si5351A, we can use one of the cheap break-out boards. I used the CJMCU-5351. Including SMA connectors, just a few bucks! I can’t really make it any cheaper, and this board also has level translators, and a 3.3 V supply, which is needed because the digital control will be running on good old 5 Volt logic. The I2C control signals are conveniently provided by a Atmel Atmega168PA controller, from a shared 5 Volt I2C bus.
Some modification is necessary – we need to remove the crystal, and add a small SMD capacitor, and a short wire. Once of the outputs, we cut the trace an re-purpose it as an input.
The schematic, it is quite similar to the connection method suggested in the Si5351 datasheet.
Actual modification and test circuit:
Obviously, to test the Si5351 over a range of reference input, we need to set the internal dividers (to lock the VCO to the reference clock input, and to divide it down to a suitable output frequency) to suitable values. Generally, 900 MHz VCO frequency, and 0.5 MHz output frequency has been selected. The low output frequency helps to see any glitches and jitter on my rather moderate scope I am using here (a 60 MHz Tektronix analog scope). At each setting, I increased the reference frequency until the Si5351 lost phase lock. Also, I reduced the power level at each frequency until some jitter showed up in the output.
The tests took more setting than expected – because the Si5351 can handle a huge range of reference frequencies – well beyond the 25 to 27 MHz, and even the internal divider can be set outside of the specified range (necessary only for the highest reference clock frequencies). A particular useful fact – the Si5351A can accept input frequencies of 100 MHz easily – I have some microwave PLLs running of a 100 MHz (rather than 10 MHz) reference.
As you can see, the internal VCO is working from about 170 to about 1100 MHz, so the 600-900 MHz is a good suggestion, but you can also run the VCO at, say, 500 or 550 MHz, if needed in some specific case of division factors (it is always much better to use integer-only divisors, rather than any fractional terms which introduce jitter and spurious signals.
After all this study, we can also plot the input sensitivity (signal from a 50 Ohm source, directly AC coupled to the XTAL A input, XTAL B floating, no other termination – probably, I will measure the characteristic impedance of the input later, no suitable test equipment currently available here in my temporary Japanese workshop).
As you can, see there is no tuned circuit or anything like it, the xtal input can accept any signal up to the highest relevant frequencies, and at lower frequencies, you just have to drive it a bit harder. 10 MHz may be the useful low limit (I suggest you drive it at 3-5 dBm when using 10 MHz, which will be about 6 dB above the sensitivity threshold).
Now, up for some long term test in the actual GPSDO application!