Squeezing out the last ppm of accuracy.

# The best solution, most likely: let the nonlinearities (INL) cancel out

After putting a bit more thought into this, let’s have a look again at the kind of nonlinearity observed for the ADS1211. We only know three points where there will be no error due to non-linearity: the zero point (because that will be covered by the zero point calibration), and the plus (and minus) voltage, at which the gain calibration is carrier out. The gain will be calibrated both for the positive and negative direction, simply by reversing the same calibration voltage, most likely, about 7.x volts, supplied by a LTZ1000.

Again, from the datasheet:

Now, what if we measure not just with one ADC, but with two, of the same kind, and hopefully, with the same non-linearity, but, with the polarity reversed. I.e., because of the fully differential nature, we can measure, simultaneously, the same voltage, both in the positive and negative direction. Doing this adequately should cancel out most of the (integral) nonlinearity. Furthermore, if use two independent references, for the two ADC we will also gain noise margin – because some of the noise in non-correlated and will cancel out – also, we will acquire the same signal independently, and do the averaging digitally! For non-correlated noise, this means about 3 dB gain, about half a bit!

It only means that finally, we will need to put in 8 ADCs to measure two voltages, but, well, who cares – the given application can handle this, specialized equipment, and no relation to the total cost. And, with some luck, it will result in linearity errors of better than 1 ppm, and 7 digits resolution, with pretty fast data rates.

The solid line: non-linearity of ADC1, the dashed line – non-linearity of ADC2, both ADC are running fully synchronized, same control codes to both ADCs. Two digital outputs – and, one output will be fully inversed, directly in the ADC controller (an ATmega32L), to yield the average of the ADC1 reading, and the complementary of ADC2. Sure the difference to 0 V can also be analyzed, to check how far off the individual values are.
The ATmega32L will also do some decimation, from 60 Hz, to maybe 5 Hz or 1 Hz (independent of the mains frequency), and sent the data to the main controlled, via an optoelectronic isolator (the full ADC section design with fully floating digital and analog grounds). 1200 or 2400 baud will be plenty to get the data out. 60 Hz 6 bytes would be 360 bytes per second, about 3600 baud (need to count start and stop bit), but with decimation, we don’t need any fast couplers, etc.

Sure, this is currently an idea, and will need a closer look, but I assume, it will do the trick, at reasonable cost.
If it works out, maybe we go one step back in the final implementation – the ADS1211 has a 4 to 1 MUX, and rather than sampling simultaneously – we might just give up the noise advantage, and sample consecutively, once with positive polarity, and then, via another channel, in inverse polarity. But hey, Texas Instruments will be happy to sell a few more ADCs.

Finally, not sure if it is better to run both ADC from the same 10 MHz clock, or from separate clocks – some of the jitter induced noise might average out only, if the jitter sources are independent. So many, option, but quite easy to find out!

# ADS1211 evaluation: a bit of shielding goes a long way…

Following-up on earlier analysis, the ADC performance observed at small decimation (like 1 s averages, with 60 Hz data rate – 60x decimation) left something to be desired – quite a few bits lost due to mains (and/or other) sinusoidal noise.

Look at 1 hour worth of data (60x decimated; each sample: 1 s worth of data), at higher magnification than before – ticks every 15 minutes:

Obiously, there are some bursts. And these are almost certainly not related to the ADC or anything internal to the circuit. Maybe the power supply, but added quite a few decoupling capacitors…

So, if the noise source is external, a bit of shielding might help – great to have a little metal box (even a steel box) at hand!

Note the 2 BNC cables – rather than one – feeding the test signals from a fully-differential source, to avoid ground loops.

Well, not much to add! Amazing what a little metal box can do!

# Studying the local characteristics of the ADS1211: ADC differential nonlinearity, missing codes

To qualify the ADS1211 for the given application, or at least, to gain some confidence in it, a test – not the for overall non-linearity (i.e., non-linearity over the full range, aka integral nonlinearity INL), but for the more detailled view at the ADC’s precision.

Local deviation of an ADC from linearity are called differential linearity, and this can be some slight deviation, or can go so far that there are even “missing codes”. A missing code is caused by a local non-linearity that is larger than 1 LSB, to the ADC will jump 2 steps, even if the voltage is only increased by 1 LSB equivalent.

First, the test setup: still the ADS1211, running at 4 MHz, 16 turbo mode, 60 Hz data rate. Connected by fully-differential coax to a (floating) source, an HPAK 8904A signal generator. This is programmed for a 5 DV output, with 20 mVpp (intentional) sine ripple, 13 Hz. The selection of the frequency is rather critical, don’t let it be anywhere close to a subharmonic or harmonic of the data rate!
The HPAK 8904A is actually really great for this purpose, you can add and mix any signals, up to 4 channels, and modulations, as desired, into one channel!

Alternatively, you could feed DC-biased noise, but these noise signals can be troublesome, and you never now what to expected in terms of amplitude, flatness, etc, unless you have really specialized gear.

Having everything set up, several hours of data were collected. Virtually no drift, so the DC component-the average ADC code (nearest integer) was subtracted from the data, and the results analyzed.

Full data, +-2000 counts is more or less +-10 mV (20 mVpp), as expected. 1 LSB is about 4 µV. There is dot for every count, even if no sample was recorded, at the given count (then, the dot is at 0 samples…).

The probability density function (PDF) corresponds to that of a sine function. That’s a good start.
Some key observations – there seem to be 3 “populations” of sample counts – codes that are “0”, i.e., missing codes; codes that have counts that are somewhat in-between (the majority), and double-counting codes. This needs some more investigation.

Taking all these data, and the know PDF of sine (of the form, 1/(x*(1-x), “bathtub curve”), the PDF was fit to the data, using least squares.

Green line shows the fit-this makes sense, and the residuals were calculated.

We are only interested in the center part, where the errors due to drift are minimal. A close up:

We can cleary see a pattern: DxMMxxMMxxMMxxMMDxMMxxMMxxMMxxMMD…
D – double code, M – missing, x – intermediate.

What seems dramatic, it’s acutally not. There aren’t any deviations more than +-1 LSB, and there will be noise and averaging anyway, to get beyond even 22 bit resolution.

# Noise: external and internal

A quick – 9 hour test – of the ADS1211: at 60 Hz data rate, 16x turbo mode. About 2 million samples.

According to the datasheet, every sample will yield about 22 bits noise free data, according to the datasheet (red circle shows setting used):

That’s what has been obtained.

Clearly visible, higher density of codes at the left and right end. Really suspicious – almost certainly, nothing else than a bit of mains feed-through, about 175 µVrms. Seems we get >20 bits, more or less, otherwise we would not be able to see the distribution (note that some counts have a positive deviation – due to non-linearity!).
But all this, with some 60 Hz noise on top…
Assuming that this noise is constant, it can be eliminated either by futher digital filtering, or by averaging/further decimation of the data, which will be done anyway. As a rule of thumb, decimation by half will give an extra 0.5 bit of data, for random noise – and a bit more for constant 60 Hz.

Here, a quick look at the decimated data (note that the sample axis ticks correspond to 2 hours time intervals):

In these diagrams, “full scale” corresponds to 20 V – the current configuration can hande up to 60 V differential signal, at 1 LSB equal 4 µV. So there is still room for improvement of resolution, like 1 LSB equal 2 µV – but this only provides useful data, if we can get noise down well below 2 µV, which will be tough anyway.

Also, quick statistical analysis, of the 10 s average – 600 sample average data:

Standard deviation, 0.71 LSB equals 0.71 LSB RMS noise, equals 3 µV. Quite reasonable!
Still visible are the two maxima of the distribution, due to the mains noise.

Comparing to a random-noise based decimation-improved resolution (noise free bits), it seems that the converter is yielding about 20 noise free bits, at 60 Hz data rate. Not quite the 22 bits mentioned in the datasheet. This is not surprising, the last 2 bits, at the fast rate, we will only be able to get this with a better, ultra low noise reference, a low-noise bias supply, and low noise analog power supply (currently using the build-in reference, and build-in bias supply, and 5 V supply from USB bus…). But fair enough, about 24 noise free bits (7.5 digits!), at 10 s averaging, and 9 hours zero point drift of less than 0.4 ppm, this might already be good enough.

# Ultralinear ADC – some mathematical review

Working a bit deeper in the topic of ADC calibration, and doing some math some preliminary conclusions reached so far:

(1) Analyzing the ADC noise, requirements to suppress mains noise, and the effective number of bits available from the ADS1211, I figure that running the ADC at 60 Hz data rate would be the best choice (50 Hz in Europe, will be factory-settable in the final apparatus), and a data volume that can be managed easily. To get the best ENOB per reading, the ADS1211 is run in 16x turbo mode, 2083 decimation, 4 MHz clock (will be 16 MHz:2 later, running on one clock with the controller, just lacking a 8 or 10 MHz crystal atm).
59.98 Hz resulting frequency, close enough. For 50 Hz, we will run at 2499 decimation, and get exactly 50 Hz data rate.
With a 4 MHz clock, about 22 bits effective resolution, with 10 MHz, even 23. Not bad, but I’m sure the test setup will be a bit worse (better reference, shielding, improved power supply needed, for the analog supply -low noise, will be based on LM723 – which is actually still a very well performing circuit, and much lower noise than the common 78xx regulators).

(2) Calibrating an ADC, to, say, 21 bit effective resolution, which two million noise-free counts, 128 dB SNR, with a sine wave by generating a histogram: it will take a long time. A very long time. 60 Hz means 5 million samples a day, would need to collect readings for several day – doesn’t seem practical.

Next steps:

(1) Noise characterization, shorted, and with a somewhat noise signal – this will tell us a bit about the nature of the local non-linarities, by comparing the noise histogram, with Gaussian noise. Will also show missing codes, if any.

(2) Do an in-depth characterization of linearity for one exemplary ADS1211, might need above-mentioned improments to reduce noise effects in the test setup, and also needs low jitter clock source (current crystal should be low jitter, but might want to change to 8 MHz before going to a lot of trouble with characterization. Key question is, for the ppm-level linearity – is this locally worse at certain codes-in certain small code regions, or evenly spread over all codes, just needing a few “pin points” for a correction algorithm, to get the linearity down to 1-2 ppm level.
After review of the literature, a method of fitting sine-wave data (similar to histogram method, but rather than just counting the bins, fitting the data – voltage vs time – to an ideal sine wave, with a 4 parameter fit, and using the residuals for non-linearity estimation; fit might be done piece-wise, for big datasets, to allow for some small frequency drift of the sine source; might also cut-off the uppermost and lowermost bins, minimum and maximum voltages).

(3) Decide, based on the data of item (2) how many measurements/level will need to be measured to continuously monitor the performance and adjust correction constant. In the final system, a 16-bit ultrahigh precision DAC/programmable voltage source. Such kind of circuit can be build from discrete low-drift low-tempco resistors like Alpha Electronics MA series, and a precision low noise/low drift reference like the LTZ1000 or LM399, and a few opams, like LTC1051.
It would be fairly easy to sample these 16 voltags with the proposed 4-ADC scheme, and calculate corrections coefficients, at the 16 points, to compensate the the major part of the non-linearity.

# Probability density function – calibrating the ADC: test run with the ADS1211

To further advance the ultra-linear ADC project, a little test setup has been deviced. Naturally, the final setup will require strict low noise construction, with only the best low-drift parts in the analog chain, and so on. At the moment, I just need to get to code running and tested to some kind of precision, therefore, a makeshift assembly will be good enough.

For the ADC, an Texas Instruments ADS1211 24-bit sigma-delta ADC, with a 4-channel MUX has been selected, simply because I have it around, and it has a good accuaracy to start with, about 15 ppm non-linearity, and no missing codes up to 22 bits.

A diagram from the datasheet, the non-linearity looks fairly well behaved – my confidence in hitting the 1 ppm mark is growing!

The ADS1211 is really a great part, for what it is, and for the price (about USD 25 each), and I have been using it a for a major projects in the past, 3 or 4 years ago.

The build in 2.5 V reference is not the most stable and quiet, but will do for now.
Input is configured for +-10 V bipolar, using 3.9 k-1 k Ubias resistors.
Clock frequency is 4 MHz, a sub-harmonic of the 16 MHz of the ATmega32L controlling it (again, the famouse JY-MCU board).

A simple trick for soldering SOIC parts to a 0.1″ pitch prototype board: just place the part on the table, upside down, and bend down, with a screwdriver, every second pin. It will be working just great, and no issue at all with soldering it, even if you don’t have good tools at hand.
No need at all for any special SMD boards, etc., just a waste of time, from my point of view.

Now, for a quick test, connected a sinewave (10 Hz), and sampled at a few Hz.
More cables than actual parts.

With the sinewave at the input, and constantly sampled, the ADC output should resemble the sine function – however, we don’t want to analyze each measurement individually, but will collect massive amounts of data, and put them into bins – looking at the sine function, not all output values have the same probability – the values at the extremes will be more frequent, because there, the sine function is more flat than close to zero. No need to give the exact maths here, just a little diagram:

In the final application, we will cut-off the outer parts, and just use the middle section. For today, that’s the result of a quick test:

Well, quite satisfactory for a start – next step will be to figure out the details (sampling rates, data transfer protocols to avoid lost samples, fast code to sort large number of samples; also, need to find out how the local varation of nonlinearity related to the larger-scale variation – by sampling for several hours…). Will all be done, step by step.
Another idea is to measure the frequency/period of the sine test signal, and using the zero-crossing as a sync pulse, to time-stamp/calculate the acutal voltage at a given time, and correlate by a least-square of similar algorithm with the ADC digital output.

# Low distortion sine generator: the source of very pure waves, digitally tunable

For the ultra-linear ADC endeavour: Generating low distortion sine waves is actually, down to about -80 dB, not really a challenge. Wien-bridge oscillators will to the job. There is a related, very popular scheme – the state variable oscillator, chiefly, SVO. It is more or less just a chain of 2 integrators, an adder, and some regulation circuitry, to keep the gain at exactly 1 and the amplitude stable. It will deliver 2 signals, at 90 degrees phase shift.

For general instruction, just have a look at the schematics of the Tektronix SG5010 Low Distortion Audio Oscillator, or the marvelous HPAKeysight 8903A Distortion Analyzer. There is also a very comprehensive article in one of the HP Journals, just have a look around the web, plenty of details out there.

For the design, I selected a UAF42AP for the integrator opamps, because this part is quite handy, and an MPY634KP analog multiplier to get the gain stable. The signal level is sensed with a simple opamp rectifier, and a damped low-pass is used for the gain stabilizer (leveler). The gain stabilizer by rectification, I just put it in as a temporary fix, lacking some analog switches (DG201) that will be used in a sample-and-hold circuit.
Also the UAF42 will be replaced later, most likely with some LME49710, which are currently resting back in Germany.

The integrator time constant of both integrator are controlled by 2 multiplying 12 bit DACs, AD7543JN. This will allow (1) tunable frequency, and (2) reduction of harmonic distortion by adjusting the tracking of the two integrators, with some inevitable differences of capacitor values, and so on. The frequency tracking will be step-wise, no change of any settings during the ADC sampling period.

A little draft (let me know if you need help reading – proper schematic to come, once design is more mature), just to help you understand:

You can see the integrators, the resistive network of the multiplying DAC, and the output. Leveler and multiplier not shown. Both signals (0 and 90 degrees) are fed to the leveler circuit, to reduce ripple a bit. Very long time constants are needed, to avoid impact of ripple on distortion – will need to analyze, and replace with a better leveler circuit (digitally controlled sample and hold, on both the 0 and 90 degree signals). The leveler circuit will also generate useful SYNC signals for the ADCs – most likely, I will link the sampling to a multiple of the calibration signal or use the SYNC signals to discard measurements over certain portions of the sine waveform.

That’s how far things have advanced. It’s running with +-15 Volts, and 5 V digital supply, and controlled by an ATmega32L via USB. Later, I might keep the ATmega, and use this as a slave controller, via a serial bus.

Measurements to come. Stay tuned.

# High resolution ADC implementation: linearity, almost perfect

At first glance, it is a straightforward request: measuring two voltages representing the cartesian corrdinates of a point, lets call the voltages Ux and Uy, and calculating the polar representation of it, the square root of the sum of squares. In fact, the later part is already irrelevant for the current topic, the only important fact is that this calculation needs to be done in a way that if Ux=13.000000 and Uy=5.000000, resulting in R=sqrt(12^2+5^2)=13.000000, is fully symmetrical for Ux and Uy, i.e., the same result must result if Ux=5.000000 and Uy=13.000000.

This can only be achieved if for both ADCs, the quantizer transfer function is perfectly identical. Simply speaking, for every voltage level applied, the resulting digital code needs to be the same, for both of the ADCs, X and Y.

A simple solution would be to use the same ADC, for both channels. However, this will increase random noise, because the integration time is only half of the available signal time. And, it is not applicable in the given case, because Ux and Uy change slowly but perfectly unpredictably over time.

Therefore, there seems to be no other way than measuring both values simultaneously, over well defined and synchronized time intervals, and then doing whatever calculation is required.
After spending 2 hours calculating, I can say, we need about 1 ppm linearity to make this work as desired, better, adding in some noise and unpredictable drift and error sources, 0.2-0.5 ppm linearity.
Also, I realized that a bit of noise would be acceptable, as long as it is coherent, and as long as it is affecting both channels in the same way. So cables and layout will be routed for as much symmetry as possible, and thermally coupled as much as possible.

How can this be achieved? First attempt, even before I learned about this issue, was to use the best ADCs at hand, two Prema 5017 7.5 digit multimeters, but even these left something to be desired (4 ppm linearity deviation per channel, but seems to be a bit better than spec).
My first suggestion was to switch from the Prema intruments, to two HPAKeysight 3458A Digital Multimeters, these reach about 0.05-0.1 ppm linearity, in the 10 V range. Impressive, but 24 kg of instruments, worth about USD 20k. Not an option, except for proof of concept, which has been achieved using the Prema devices.

Now, what kind of intricate sampling scheme could be used to make this work, with off-the-shelf parts. Well, first we need a good starting point, a linear ADC. Looking through the various datasheets, let’s discuss a particular part, with impressive performance ratings, the AD7710. This is a 24 bit sigma-delta converter, and has +-15 ppm nonlinearity. So we need to find means to improve this by a factor of, say, 30 to 50. Seems to be viable, with some error correction meachanism. Also, we don’t want the error correction to cause any dead time of the system (i.e., there can’t be an autocalibration feature taking significant time, leaving gaps in the signal measurement).

So, here is the proposed scheme:

It’s a bit rough, buta acutally, not too complicated. What we intend to do is to use 4 ADCs (named A, B, C, D) rather than two, and to use ADCs that have a build-in 2 to 1 MUX, so it can either sample channel 1 or channel 2. The “1” channels, A-1, B-1, C-1 and D-1 are connected to a reference source that will allow analysis on ADC non-linearity, and the “2” channel, well, thats for the acutal X and Y signals.

The whole thing is connected to a CPU, which will require some kbytes of RAM and FFT/histogram processing powder, not an issue these days. It will acquire the digital representations Q'(X) and Q'(Y), and hold the non-linearity information for each of the ADCs (called “linearity tables”, LIN A trough LIN D) and use this data to calculate the corrected “ultra-linear” digital representations of the input voltages, Q(X), and Q(Y).

Don’t ask how I will calculate the non-linear correction coefficients. It’s filling piles of paper already, working through FFT and histrogram analysis, and might be some occupation for an upcoming rainy Saturday, to get this coded.

The sampling scheme will work with two steps: measuring a cal signal on A and C, and measuring X and Y on B and D; then, 2nd step, B and D cal signal, A and C – X and Y signal.

Next question, what is a suitable cal signal that can be samples to yield the non-linear properties. Well, as we are only interested in the relative non-linearities of the converters, there is more freedom to choose signals, e.g., a triangular signal, or a ramp function. But, as you might know, it’s not all that easy to generate a good linear ramp voltage – there capacitors involved, and opamp integrators, and we are talking low frequency here, lika a cal signal frequency of 10 Hz, and measurement periods of minutes, rather than seconds. This will make leakage current significant, and a lot of effort. And, we run the risk of introducing some second-order errors, so perferably, the correction scheme employed should acutally yield quantizer transfer functions of all ADCs that are as close to ideal linearity as possible.

So, what signal to use. The solution is simple – we need a perfectly clean sine wave. This is predictable with time, easy to handle numerically, and, fairly easy to generate. For reasons of filtering, preferably, noise and distortion of the signal should be minimal. But, how much is minimal?
We will treat the signals, cal, X, Y, as a dynamic signals (slow, but steadily changing, with R, see above, having certain very low frequency components that we want to extract).

Some numbers: say, we want to resolve 2 volts to about 1 µV, that’s a resolution of about 2 million counts, in bits, 21 significant bits of information. This corresponds to a dynamic range of about 20*log10(2^21)=127 dB. Cross-check against the AD7710 datasheet shows that this is possible, for both dynamic and essentially-DC input conditions (with effective resolution of about 22 bits at 10 Hz sample rate). By averaging, to 2.5 Hz, we might win 1 bit, and get about 23 bits of useful information. That’s all falling into place; actually, it might even be better to sample at a faster rate, and do more digital averaging – this needs to be figured out later.

The ADC interfacing, at least the digital end, will be easy, just a few wires. The analog front end – also not too difficult, the AD7710 has a build in MUX, differential input, and the X and Y signals are available as low-impedance, very low noise signals. I might in fact put the 4 AD7710 in a little metal case, solder it all free-wire, and encapsulate it with a thermally conductive epoxy potting compound.

Next step will be to fabricate a low distortion cal source, of variable frequency. Frequency needs to be digitally settable, not too very accurate steps, but close enough, to keep it constant within drift and eventual changes of sampling rates/”integration times”.
Following above estimation, the distortion of this should be somewhere around -100 dB. It doesn’t need to be -130 dB, because some deviation of the transfer functions from ideal linearity will be acceptable in the given case – if anyone needs better linearity, just add a better signal source, keep the ADC setup thermostated -the limit will be only the stability of the non-linearity with time.
Well, -100 dB might be a bit tough to proof with the equipment I have around here, and with the relatively plain parts. Let’s see what is possible. And maybe build an improved version later.