Fractional-N PLL for the Micro-Tel 1295: ADF4157/ADF5002

After spending most of the day at the beach, some more experimentation – with a fractional-N approach. Two little chips were around from another project, why not give it a try:

(1) The Analog Devices ADF4157, 6 GHz, 25 bit fixed modulus fractional-N PLL – this part is really great, for many purposes. It’s more or less pure magic what these folks at Analog do and achieve.

(2) To make it work up to 18 GHz, a prescaler is needed. Well, unfortunatly, I only have a :8 prescaler (ADF5002) around – this will give 0.25 to 2.25 GHz, for the 2 to 18 GHz input. Not quite ideal, because at 2 GHz it’s getting really into low frequencies for the ADF4157, and the output power of the ADF5002, which is a more-than-sufficient -5 dBm in the 4 to 18 GHz, range, but dropping off to only about -10 dBm at 2 GHz. At the same time, RF input sensitivity of the ADF4157 drops considerably for input frequencies below 0.5 GHz… we will see.

Some calculations:
With a 10 MHz reference clock, and the phase detector frequency set to 1.25 MHz (reference divider=8), this will result in 10 MHz steps, with 2^25 spacings in between. This gives about 0.298 Hz resolution. And moreover, with this setting, 10 MHz steps are possible, with no fractional-N divisor (which can always lead so some rather unpredictable fractional-N spurs).

The circuit – there is no big secret to it, a 5k1 reference resistor to set the charge pump current to 5 mA, and a few 6k8 resistors (0805 SMD) to make the chip compatible to a 5 V digital world. Two SMA connectors – one for the signal, and one for the 10 MHz reference. All wiring is done with 0.08 mm tinned copper wire… hope you have a steady hand. With a drop of epoxy glue, everything is held in place and well-protected.



Tests will follow – currently the loop bandwidth tests are running for the 1295, with the ADF41020 PLL.

Noise and spurs, ADF41020/Micro-Tel SG-811 PLL

After getting things worked out with the loop filter, some quick check for spurious responses. To do such analysis near the noise level, a FFT/dynamic signal analyzer can be used, but I find it somewhat troublesome, and rather use a swept frequency analyzer for any such work that goes beyond 1 kHz. Below 1 kHz, the FFT is hard to beat. One of the few exemptions is the HPAK 3585A spectrum analyzer, which covers from about DC to 40 MHz, and has resolution bandwidth filters of down to 3 Hz (discrete hardware, not software filters), with baseline at -135 dBm, or lower.

The 3585A doing its thing…

The results – 1 to 500 Hz
348_00_0001 to 05
Mainly 60 Hz harmonics – well, will need to keep the cables short (especially the coarse tune cables) and everything far away from mains transformers.

10 Hz to 5 kHz
348_00_001 to 5
Signal at 1 kHz is about -70 dBm, not much. No spurs.

5 to 30 kHz
348_00_5 to 30
Two unexpected spurs – 1st: 19.986 – this is an artifact of the 3585A. 2nd: 18766, this seems unreleated to the PLL (doesn’t change with frequency or divider settings), maybe some switchmode supply stray. Well, down below -100 dBm.

25 kHz (with some 60 Hz harmonic sidebands, -115 dBm) – reference spur, about -93 dBm.
25 khz spur detail

All in all, with some refinement of the software, and a bit of mechanical work to get this all mounted into a nice case, the setup should work find and provide great service.
Sure enough, some direct phase noise measurements on the SG-811 output will eventually follow, once the opportunity is right and the equipment at hand.

Micro-Tel SG-811/ADF41020 PLL: working out the details – loop filter, bandwidth, charge pump currents

Designing a stable PLL is not really a big challenge, with all the simulation tools available, and after you have mastered some basic experiments with the 4046 chip, or similar circuits. For PLL simulation software, I suggest to look at ADIsimPLL, available free of charge, from Analog Devices.
However, stable doesn’t necessarily mean wideband, and exhibiting similar characteristics over a full 2 to 18 GHz band. That’s what we want to achieve here.

First some targets – after reviewing the circuits of the Micro-Tel SG-811/1295, and looking at the stability of the build-in YIGs, I figured that a good PLL bandwidth for this system would be somewhere in the 200-500 Hz region. This would still allow to correct for some mains-induced frequency fluctuations (50/60 Hz), and the frequencies are well below the 25 kHz phase detector frequency used for the ADF41020. Furthermore, the bandwidth should be reasonably stable of the full range of frequencies, with no need to use multiple loop filters, or troublesome switchable capacitors/variable gain amplifiers – all should be operated from a single-ended 15V power supply, to provide 0-10 V for the Micro-Tel 1295, and 0-3 V for the SG-811, from a single little board.

With this in mind, an OPA284 rail-to-rail precision amplifier (low noise, 4 MHz BW, can drive +-6.5 mA) was selected as the active part, and some capacitors (only use good quality capacitors, polymer dielectric, or stable ceramic capacitors, NPO) and resistors put together. There is only one adjustment, the damping resistor in the feedback loop.

Sketch of the schematic
adf41020 sg-811 pll loop filter

How to figure out the loop characteristics? Many pages have been written about this, determining open-loop gains and phase margins, etc., but how to approach this in practice, one you have done the calculations and figured out a setup that basically works? This is where the extra resistor and the two test points (A, B, see schematic) come into play. The resistor close to the output (8k2, this is just a temporary part, only inserted during test – bridged with a piece of view during normal operation) is used to isolate the loop output, from the SG-811 phase lock input (which is nothing else than a heavy VCO=voltage controlled oscillator). A few extra parts are also connected to feed a test signal to the VCO, in addition to the loop filter output voltage.
This test port is intended to disturb the PLL just a bit, without causing loss of phase lock, and measure the response. Such work is best done with a dynamic signal analyzer – I’m using a HPAK 3562a, not because it is the latest model, but because that’s what I have around here in my temporary workshop. It had the old CRT replaced by a nice color LCD screen, and it features a very acceptable noise floor, and gain/phases analysis.

The test setup (please excuse the mess, not too much empty bench space around here)
pll loop test - micro-tel sg-811 - adf41020

Now we just need to work through various frequencies and settings, to better understand the characteristics of the system.
To cover all the YIGs and bands of the SG-811 (which might have unknown variations in tuning sensitivity, noise, etc.), frequencies around 2, 6, 10, 12.5 and 17.5 GHz were chosen for the test (exact values can be found in the worksheet, better not to use even values, e.g., 2.0000 GHz, but to exercise the divider circuits – to see if there are any spurs).

At each frequency, magnitude and phase response was collected, examples:
Gain (disregard the unstable response below 10 Hz, just an artifact)


The interesting point is the 0 dB crossing of the gain trace – the unity gain bandwidth. This is determined for each test condition, and then the corresponding phase is obtained from the phase plot. In this example, BW_0dB is about 380 Hz, with about 20 degrees phase. Why is it so important? Simply because we need to keep this phase gap (of the A and B signals) well above 0 degrees, otherwise, the loop will become unstable-oscillate-massive phase noise of the generator will result.

Some call this the phase margin, so do I, although the whole discussion about gain and phase margins is typically centered around open-loop system, whereas we are dealing with a closed loop here. Fair enough.

Now, after some measurements, and number crunching, the results:

Phase vs. BW, at various frequencies
pm vs bw sg-811 pll
-you can see, the phase margin is virtually independent of frequency, and purely a function of bandwidth. So we can limit all further discussion to bandwidth, and don’t need to worry about phase margin separately. It is also clear from this diagram that we should better stay in the 250-300 Hz bandwidth region, for the given filter, to keep the phase margin above 25 degrees, which is a reasonable value.

Now, how to keep the bandwidth stable with all the frequencies and YIGs/SG-811 bands and sensitivities changing? Fortunately, the ADF41020 has a nice build-in function: the charge pump current can be set in 8 steps (0 to 7), from 0.625 to 5 mA (for a 5k1 reference resistor) – and setting the charge pump current (Icp) is not much else than changing the gain of the loop filter. The gain, in turn, will change the 0 dB bandwidth in a fairly linear fashion. Note: typically, the adjustable charge pump current is used to improve locking speed – at wider bandwidth, and mainly, for fixed-frequency applications – but is is also a very useful feature to keep bandwidth stable, for PLL circuits that need to cover a wide range of frequencies, like in the case of the SG-811.

The next result – bandwidth vs. Icp setpoint
sg-811 pll bw vs charge pump current at various frequencies
-looking at this diagram, the bandwidth is not only a function of Icp, but also a function of frequency. For the larger frequencies, the bandwidth is much lower. Some calculations, and it turns out that the product of bandwidth, multiplied with frequency to the power of 0.7 (a bit more than the squareroot) is a good parameter that gives an almost linear vs. Icp (see worksheet, if interested).
adf41020 pll bw phase margin

After all the measurements, things are now pretty clear – if we set the Icp current right, BW can be kept stable, over almost the full range, without any extra parts and switches, and about 300 Hz seems to be a reasonable compromise of PLL speed and stability.

Estimated PLL bandwidth (0 dB), using the Icp current adjustment of the ADF41020
bw vs frq with charge pump current adjustment
At the lowest frequencies (2 GHz range), the BW is found a bit larger than desired, but still, the loop still has 20 degrees margin.

Well, with all the phase margins and uncertainties, is the loop really stable enough? To check this out, what is typically done is to first try a few odd frequencies, at the start, end and in the middle of each band and monitor the VCO control voltage with a scope, for any oscillations or otherwise strange behavior. Then try a few small frequency steps, and see how the loop settles. This all went without any issues.

Still, to be sure, especially close to 2 GHz (increased bandwidth), a test was performed by injecting a 100 mV (nominal) squarewave, 10 Hz, via the test port mentioned above. The loop output spectra showed that this worked, and that the 10 Hz contribution is significant, while still not swamping everything else and driving the loop out of lock right away.

Power spectra with test signal on (upper diagram), and off (lower diagram).
pll power spectra

There are some 60 Hz/harmonic 60 Hz spurs, mainly due to coupling of 60 Hz to the coarse tune line, which is just a plain coax cable that doesn’t provide any good shielding vs. 60 Hz (or 50 Hz, in Europe) interference.

Needless to say, the PLL will not stop working right away when the phase hits 0 deg at the 0 dB point (see above, phase margin vs. bandwidth plot – even at negative phase, measurement was still possible – as long as the amplitude of the test signal is kept small).
There will be signs of instability, and this is what this test reveals. So the frequency was set again to 2.2221 GHz, and the charge pump current Icp increase step by step, from 0 to 5. At 6 and 7, no phase lock could be achieve – fully unstable loop.

Step response (AC component only, square wave, 10 Hz at nominal 100 mV, supplied to test port)
pll step response 2.2221 ghz 100 mV
Icp=0 – this is the most stable condition, phase margin is about 20 degrees. Already at Icp=1, phase margin of about 3 degrees, stability is much compromised/considerably more noise, not only for the step response, but also during the steady portions. At Icp=2 and above, phase margin is negative, still, phase lock is robust (will not re-lock, once lock is lost), and the pulse response suggests to stay away from such regions.

Micro-Tel SG-811 PLL – phase lock achieved!

Thanks to a rainy late afternoon (and evening), some success with getting the SG-811 signal generator phase locked. For external frequency control, the SG-811 needs a coarse tune voltage, to adjust the frequency to within a few MHz of the target. This is done using a DAC8830(=MAX541) 16 bit DAC and OP284 opamp to scale the 0 to 2.5 V of the DAC to 0 to 10 V required for the coarse tune input of the SG-811.

The SG-811 is run at a level of +5 dBm, and a directional coupler is used to get a sample of this signal (about -5 dBm) into a ADF41020 single chip PLL. The remainder of the signal is fed into a EIP 454A microwave counter, which also provides a 10 MHz reference for the PLL.

First, it turned out that the SG-811 uses a different voltage range (-3 to 3 V) for the phase lock input, compared to the Micro-Tel 1295 (0 to 10 V). So the 8904A was used to determine the phase lock input sensitivity (deviation in MHz per Volt). Some existing AVR code (the whole setup is controlled by an ATMega32L) was modified to fit the SG-811 requirements. This code has some nice features, including a self-adjusting coarse tune voltage. This is of great help because the phase lock input of the SG-811 only allows for a few MHz frequency shift, and during warm-up the generator can easily drift out of the lock window, if the coarse tune value is left unadjusted. Obviously, the coarse tune voltage is changed in very small steps, 1 LSB at a time.
Drop me a line if you are interested in more details.

The (temporary) test setup, set to an arbitrary value of 4.5500 GHz.

The control circuitry
Display shows (second line): Divider values of the PLL, DAC coarse tune value (0 to 65535), band, and phase control voltage (deviation from mid-point in mV, +-100 mV are perfectly fine, if +-50 mV are reached with drift correction activated, the DAC coarse tune will be automatically adjusted to get the phase control voltage back to less than +-10 mV).

Last but not least, also the shift register board, 3x LS164 (for remotely controlling the band switches) has been connected to the AVR micro, and all is functional.

Solid state Tesla coil – aka “Plasma speaker”

This is really a nice project that any serious electronics hobbyist should tackle, or rather not, because it’s really dangerous, uses mains voltages, and emits undue amounts of RF radiation non-complient with all common regulations.
So please, take this for educational purposes only, don’t try at home, unless you are fully qualified, and have a shielded room, with no RF leakage to the outside world.

The test setup

The coil

The coil is made of about 0.3 mm copper wire (magnet wire), and resonant at pretty much exactly 250 kHz. A 2″ aluminum duct is used as terminal capacity, bent to a toroidal shape.

The circuit – it’s pretty basic. A SG3524 is used as the driver, with a 10-turn pot to adjust the frequency (to resonance). A small bit of FM (frequency modulation) can be provided from by an audio signal, fed via a pair of Cinch connector (sorry, no stereo – both channels are combined internally) – turning the solid state Tesla coil into a “plasma speaker”. You can hear the sound of your favorite song, played by hissing sparks, if you dare to hook-up you MP3 player to this apparatus (use a long cable, and an inexpensive player; don’t touch the player, when the coil is energized – you will radiate far too much RF into it!).
The SG3524 output is used to feed a gate drive transformer, which in turn drive the MOSFETs (2 pcs IRFP450, 500 V – 0.4 Ohm – 14 A). The low voltage part/driver is power by a little transformer, the IRFPs are connected directly to a DC voltage derived from the mains input, about 300 Volt (operating from 230 VAC in Europe). Don’t touch the primary winding!
Some VDRs, capacitors and diodes are used to keep transients away, and to keep it running stable.

The final device – it’s working great, but don’t have pictures at hand – will provide later! As I said, don’t try this at home, but I will gladly answer any of your questions.


I can tell you, these sparks are quite noisy! Keep you children (and yourself) at a safe distance!
Never attempt to energize such apparatus at your home!


With the given 0.5 mA supply, there is a spark every few seconds. Triggering is nice, and stage voltage reaches about 23-24 kV – the design limit.

Should you ever operate a Marx generator, make sure to properly ground and short it prior to approaching it any closer than a few feet!

Stage design

Some boundary conditions:

(1) Stage voltage equals charge voltage – 20-25 kV range would be most suitable to fit an easy-to-build flyback transformer type supply.

(2) Discharge energy should be at least 10 Joules, otherwise, there is not enough noise and the thing doesn’t look and feel dangerous enough (you might as well use a piezo fire lighter to make some sparks…)

(3) Charge time should be reasonable, not more than a few seconds.

With 16 0.1 µF capacitors, rated for 1.6 kV and operated at 1.5 kV (24 kV per stage), a design was established that uses 10 stages – about 220-230 kV peak voltage. This results in about 20 Joules of discharge energy.
It was also found that there is no need to make the stage charging resistors very large (some sources suggest multiple Megaohms, 1 M is just fine for most of the designs relevant in this context). A value of about 8 M was determined for the charge resistor – mostly because of the 0.5 mA current limit of the power supply – you can use a lower value, if you want to put more current into the Marx. But remember that a high-value charge resistor will also protect the rectifier cascade of you power supply, so you might not want to take too big risks.

Detail view

For the spark gap – these are the approximate voltage for a gap mm:
voltage vs gap

Accordingly, the gaps were adjusted to about 8.5 mm using a plastic gauge (to avoid scratching of the spheres).
Note that the stage carrier plates have cut-outs at the spark gaps! This is to avoid unwanted discharge, but also to ensure line-of-sight contact of the spark gaps, which ensures stable triggering (because of UV radiation, emitted from one gap, lowering the spark cap threshold voltage of the next).

Full view
(in the back, you can see an earlier experimental model, using Wima FKP-1 capacitors – however, this design added a lot of inductance, and the adjustment of the spark gaps was not thought out very well).

The starting point

What is a Marx generator – essentially, a device that lets you charge a set of capacitors in parallel (say, to 24 kV), and then discharge they in series, say, at 240 kV, if you have 10 capacitors. There is much more theory to it, all has been very well described elsewhere since the times of Mr. Marx, who first deviced such circuits, arguably, in 1923. If you need more explanation – please ask, I will be glad to explain it to you.

To build a nice Marx generator, you need a few parts:

(1) High voltage resistors – don’t assume this is the easy part – the resistors need to be able to withstand quite some voltage, several kV, and high discharge energy-changes in potential. Carbon composite resistors are best for such applications, but rate to find nowadays. You can get away with series connection of some high-value metal oxide layer transistors. I used some Vitrohm 1 M (Megaohm), 7.5 kV rated resistors obtained as NOS (now-old-stock; series 176 – could not find any data, but seem reasonably robust), some current/more widely available types that may be suitable: Vishay 0207 High Pulse Load Resistors (2 in series), or similar, successfully used for similar projects of more serious nature.

(2) Capacitors – also these must be not only be designed for high voltage, but also pulse rated. Best are especially made pulse discharge capacitors – but these often are oil-filled, rare, and too big for the given purpose. Best alternatives are PP type film capacitors, like the Wima FKP-1 or FKP-4. I used Vishay MKP1841, 0.1 µF 1.6 kV capacitors, metallized PP. The spec to look for is the maximal pulse rise time – the 1841s are not too bad, at least, good enough for this project, and a large bag could be sourced at low cost.

(3) Spark gaps – these need to trigger precisely, otherwise, the apparatus won’t work at full performance, or constantly misfire. Best use polished stainless steel spheres, about 15-20 mm diameter, readly available, already threaded, and easy to attach to the stages.

(4) Some hardware – isolating stand-offs, and some isolating sheet material for the stags – I used some FR4 glass fibre-epoxy boards (leftovers from failed printed circuits, with the copper fully stripped).

(5) A high voltage supply and a feed resistor (about 3-10 M, capable to withstanding at least 50 kV). A series of resistors, item 1, mounted along a plastic rod (Plexiglass, or the like) will do. For the supply, this needs to provide about 20-25 kV (make sure it doesn’t provide more, otherwise the capacitors will suffer!), about 0.5 mA. A fly-back transformer based supply. I’m use a regulated supply (TL494 switchmode regulator, flyback transformer), so the stage charge voltage can be adjusted precisely, and no risk to damage anything.

(6) A good ground connection (earth conductor). Never use plain mains ground, if you don’t want to damage your home electronics! Anything will do, like a water pipe (if fully metallic down to the inlet), or a heating pipe).

(7) Plenty of ground wires around that you can use to safely discharge the apparatus and to keep it shorted to ground if not in use. RISK OF ELECTRIC SHOCK! ALWAYS SHORT THIS APPARATUS WHEN NOT IN USE!

The current regulator

The current regulator – this module converts the current setpoint signal (from the position regulator) into a drive current for the magnet coil. This is achieved using a TL494 PWM modulator chip, and two BUZ11A (50 V – 0.045 Ohm – 26 A) MOSFETs, each operated at 50% duty.


Brief description:
The current setpoint signal is connected to JP1-9, connected to one of the comparators of IC2, the TL494. The other comparator is used as a current limiter: the sense wires of a 0.05 Ohm shunt in the coil supply line are connected to the input of IC1, and intrumentational amplifier, via JP1-7 and JP1-8. You might have to change the amplifier gain by modification of R5.
Current setpoint is adjusted by trimmer R14. JP1-3 and JP-4 provide the gate drive for the two BUZ11A MOSFETs. The drains are connected to the coil, the sources are joined at the current shunt.
Directly, at the MOSFETs, which are mounted on a heatshink (but don’t actually get hot), together with current shunt, there are several electrolytic capacitors (low ESR type), and a 1 µF PP cap (polypropylene dielectric, for pulse current service) in parallel with the (non-regulated) magnet supply. In combination with a strong and fast Schottky diode (anode at the MOSFETs, cathode a the positive supply), these caps are the best protection against any transient voltages when the coil is de-energized.

SimonsDialogs – A wild collection of random thoughts, observations and learnings. Presented by Simon.