Tag Archives: ADF41020

ADF41020 18 GHz PLL: universal divider and PLL board

I cannot praise Analog Devices enough for the ingenious designs, and for providing parts like the ADF41020, a fully integrated 18 GHz PLL. This is actually part of a major design effort for a multi-channel frontend, here just a description of the small test board used to establish the general circuit layout and board design.

Probably interesting is also the hand-soldering of the LFCSP leadframe package, which is actually not as difficult as it seems. For soldering of the pad, there is a large via in the center, which does provide good heat-sinking and is easy to solder through the 1.2 mm board.

pll18d0 layout

Above, the layout, below, 10 boards – 14 dollars and a few weeks later.

pll18d0 pcbs

For soldering, best use 0.5 mm Ag-containing SMD solder, with Type 32 flux, which is halogen free resin flux.

pll18d0 solder

To mount the LFCSP, first apply some solder to the chip pads, but not to the center/heat sink pad. Apply some flux to the board (which is already pre-tinned; use any good SMD flux pen). Then align with a good magnifier, using some Kapton tape to hold the chip in place – leave one side exposed. Then solder, in one stroke, using a medium hot soldering tip. Reflow another time – one side done. Remove the Kapton tape, and solder the remaining 3 sides. Then stick down the chip with Kapton tape again (to avoid any remote chance of movement, in case all the solder melts during the next step). Turn around the boards, and solder through the via, with a fine solder tip.

pll18d0 via

pll18d0 adf41020 mounted

pll18d0 full board

For a test, just apply a test signal to the input, and use the “MUX” output to check for any pulses. There we go:

pll18d0 2215 pulses

These pulses aren’t quite long, so it is one of the few occasions where a scope more advanced than the 2215 Tektronix is really useful in the home shop… same pulses on a HP/Agilent/Keysight 54720A, 54713B plug-in, and 100 MHz 1:10 probe.

pll18d0 pulse out

These fast risetime pulses, and the various prescalers, dividers and good input sensitivity make the ADF41020 quite useful for any PLL and frequency counting applications.

pll18d0 2ghz in 25 khz out

2 GHz in, 25 kHz out — confirmed.

About the input sensitivity: the ADF41020 is specified over a 4 to 18 GHz range – how about lower frequencies? A quick look at the input circuit shows a 3 pF capacitor – which equals a reactance of about 53 Ohms, at 1 GHz (i.e., the capacitor and termination resistor will cut the input power available to the buffer approximately in half).

pll18d0 rf input

pll18d0 input sens

… quite useful down to 1 GHz, no problem or instability at all. Also checked the the reproducibility, for 3 devices – not a lot of scatter.

Tripple PLL Controller, for Micro-Tel SG-811/1295/1295: converting a ratsnest to a shiny box

Comming back to an earlier project, the frequency stabilizers/PLL controls for the Micro-Tel 1295 receiver (2 pcs, one for through, and one for reflected power), and the Micro-Tel SG-811 generator (0.01-18 GHz).
The setup has been working well, but it is an awful mess of cables, as a result of the development process.

18 ghz pll wire mess

Now is a good time to finalize the circuit, and to put it into a nice case.

pll controller case

This is the front panel – the back panel has numerous BNC connectors, for the “PLL Phase Lock” voltage, and the “Frequency Control”, i.e., coarse tune voltage. The latter voltages, 3x 0-10 Volts, are generated by a DAC board, which is now ready and tested. Not a thing of beauty, but it works, and no reason to assemble another one just to clean things up a bit.

dac board

The circuit is reasonably straightforward, a 2.5 V precision reference is used, and three MAX541 16 bit DACs, followed by OP284 amplifier to convert the signal to the 0-10 V range.
The MAX541, it’s a really great part, full 16 bits, +-1 bit integral nonlinearity, and very stable over temperature and time. Highly recommended for any precision application.
One of the channels has an additional TLC2201 opamp, which is there more for historic reasons than for anything else.

dac board schematic

The PLLs use three ADF41020 18 GHz chips, following the approach discussed earlier. This will give 100 kHz frequency resolution, which is more than sufficient for the intended purpose of measuring gain/attenuation and SWR over the full range of microwave frequencies up to 18 GHz, or 40 GHz, if no SWR measurement is required.

The 10 MHz reference circuit has also been completed, and is working well, converting a 10 MHz input signal (of more or less arbitray shape and amplitude) to 3x 10 MHz REF signals for the ADF41020, and two 5 MHz outputs, for the 1295 receivers, just in case I need to work with external downconversion-the 5 MHz signal is only affecting the 0.01-2 GHz range of frequencies. Well, why not having everything phase locked, if we can.

10 mhz 5 mhz ref circuit schematic

The 10 MHz circuit has been modified slighly, to accept 1 kOhm impedance 10 MHz input signals, which are rather common for instrumentation purposes. Some caps and protection circuitry has been added, output levels are just about 0 dBm. No need to go to stronger signals, it will only cause spurious response, and other trouble, because shielding inside of the PLL case won’t be very strong.

Some remaining work, before we can call this project complete:

(1) A power supply regulator, +5, +3, +3 (Vp low noise), +15, +20 supply has been build, but need to be mounted to the case, for heat sinking. This will need to wait for a few weeks, need to wait for some travel to Germany coming up, where the metal working machinery resides.

(2) Digital interface and cables for band control of the SG-811, and the two 1295s are complete, just need to be mounted and tested.

(3) Relais control module needs to be designed and build – there are two 18 GHz transfer switches (one is needed for basic functionality, a second one for the various unexpected test configurations). The transfer switches are HP 8763B, see earlier post. These are wonderfully precise and repeatable, albeit, list price is about USD 1k, each.

(4) Need to route the two serial signals (dB reading, signal strength) from the Micro-Tel 1295 to the ATMega32L, which only one USART input – no problem, because this is all TTL-level USART signals, but need to get a multiplexer/a few NAND gates to set this up. Currently, only one 1295 can be recorded at a time, which means, either gain or SWR measurement.

(5) Sure, the software, both firmware and instrument control software will need to be refined and consolidated. All PLL calculations and adjustments are done within the ATMega32L, still there is a need for a more convenient user interface than just command line.

… to be continued!

PLL characterization – final results for the Micro-Tel SG-811 and Micro-Tel 1295 circuits

After some experimentation, measurements, etc. – as described before, time to wrap it up.

The PLL loop filter output is now connected to the phase lock input (the additional 1 k/100 n low pass in the earlier schematic has been omitted), with a 330 Ohm resistor in series. This will remain in the circuit, because it’s handy to characterize the loop, and to provide a bit of protection for the opamp output, in case something goes wrong, to give it a chance to survive.

With the charge pump current adjustments now implemented in the software, that’s the result, all pretty stable and constant over the full range.

The SG-811 signal source
micro-tel sg-811 pll bandwith vs frequency

The 1295 receiver
micro-tel 1295 pll bandwidth vs frequency

Micro-Tel SG-811 PLL: frequency response
Gain
sg-811 final gain

Phase
sg-811 final phase

Micro-Tel 1295: frequency response
Gain
1295 pll final gain

Phase
1295 pll final phase

PLL measurements continued… ADF41020 locking the Micro-Tel 1295

With the work on the Micro-Tel SG-811 generator PLL mostly completed, some trials with the Micro-Tel 1295 receiver – this instrument has similar YIGs fitted, just needs to be tuned 30 MHz above the actual frequency tuned, because the 1295 is running on a 30 MHz IF (all diagrams have tuned frequencies, not LO frequencies).

After some crude analysis of the schematics, the 1295 seems to be able to handle a bit more PLL bandwidth – so the target set more in the 500 Hz to 1 kHz region, and some calculations were carried out with the ADIsimPLL program, to determine the rough capacitor and resistor values – otherwise, the loop filter is the same as for the SG-811 PLL, also using an OPA284 opamp.

Otherwise, pretty much comparable results (earlier post related to the SG-811), for example (17.8141 GHz tuned/17.8171 GHz LO frequency, Icp setting 6):

Gain (disregard 1 to 10 Hz)
micro-tel 1295 17814100 kHz cpc6 gain

Phase
micro-tel 1295 17814100 kHz cpc6 phase

After quite a few of these measurement (doesn’t actually take too long), the results.
adf41020 pll bw phase margin 1295

Phase margin vs. bandwidth
pm vs bw adf41020 micro-tel 1295

Bandwidth vs. charge pump current Icp setting, at various frequencies
bw vs icp at various frq adf41020 micr-tel 1295 pll

Again, a bandwidth frequency^0.7 product could be used to get the numbers down to two parameters – slope and intercept of the bandwidth*frequency^0.7 vs. Icp setting curve.
Finally, suitable Icp settings for a 600 Hz target BW:
bw vs frq adf41020 micro-tel 1295 with Icp adjustment

The result seems quite satisfactory, pretty much constant 600 Hz BW can be achieved over the full 2 to 18 Ghz range, at about 47 degrees phase margin. This should allow for stable operation. No locking issues were observed at any of the frequencies, even with full Icp current.

Noise and spurs, ADF41020/Micro-Tel SG-811 PLL

After getting things worked out with the loop filter, some quick check for spurious responses. To do such analysis near the noise level, a FFT/dynamic signal analyzer can be used, but I find it somewhat troublesome, and rather use a swept frequency analyzer for any such work that goes beyond 1 kHz. Below 1 kHz, the FFT is hard to beat. One of the few exemptions is the HPAK 3585A spectrum analyzer, which covers from about DC to 40 MHz, and has resolution bandwidth filters of down to 3 Hz (discrete hardware, not software filters), with baseline at -135 dBm, or lower.

The 3585A doing its thing…
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The results – 1 to 500 Hz
348_00_0001 to 05
Mainly 60 Hz harmonics – well, will need to keep the cables short (especially the coarse tune cables) and everything far away from mains transformers.

10 Hz to 5 kHz
348_00_001 to 5
Signal at 1 kHz is about -70 dBm, not much. No spurs.

5 to 30 kHz
348_00_5 to 30
Two unexpected spurs – 1st: 19.986 – this is an artifact of the 3585A. 2nd: 18766, this seems unreleated to the PLL (doesn’t change with frequency or divider settings), maybe some switchmode supply stray. Well, down below -100 dBm.

25 kHz (with some 60 Hz harmonic sidebands, -115 dBm) – reference spur, about -93 dBm.
25 khz spur detail

All in all, with some refinement of the software, and a bit of mechanical work to get this all mounted into a nice case, the setup should work find and provide great service.
Sure enough, some direct phase noise measurements on the SG-811 output will eventually follow, once the opportunity is right and the equipment at hand.

Micro-Tel SG-811/ADF41020 PLL: working out the details – loop filter, bandwidth, charge pump currents

Designing a stable PLL is not really a big challenge, with all the simulation tools available, and after you have mastered some basic experiments with the 4046 chip, or similar circuits. For PLL simulation software, I suggest to look at ADIsimPLL, available free of charge, from Analog Devices.
However, stable doesn’t necessarily mean wideband, and exhibiting similar characteristics over a full 2 to 18 GHz band. That’s what we want to achieve here.

First some targets – after reviewing the circuits of the Micro-Tel SG-811/1295, and looking at the stability of the build-in YIGs, I figured that a good PLL bandwidth for this system would be somewhere in the 200-500 Hz region. This would still allow to correct for some mains-induced frequency fluctuations (50/60 Hz), and the frequencies are well below the 25 kHz phase detector frequency used for the ADF41020. Furthermore, the bandwidth should be reasonably stable of the full range of frequencies, with no need to use multiple loop filters, or troublesome switchable capacitors/variable gain amplifiers – all should be operated from a single-ended 15V power supply, to provide 0-10 V for the Micro-Tel 1295, and 0-3 V for the SG-811, from a single little board.

With this in mind, an OPA284 rail-to-rail precision amplifier (low noise, 4 MHz BW, can drive +-6.5 mA) was selected as the active part, and some capacitors (only use good quality capacitors, polymer dielectric, or stable ceramic capacitors, NPO) and resistors put together. There is only one adjustment, the damping resistor in the feedback loop.

Sketch of the schematic
adf41020 sg-811 pll loop filter

How to figure out the loop characteristics? Many pages have been written about this, determining open-loop gains and phase margins, etc., but how to approach this in practice, one you have done the calculations and figured out a setup that basically works? This is where the extra resistor and the two test points (A, B, see schematic) come into play. The resistor close to the output (8k2, this is just a temporary part, only inserted during test – bridged with a piece of view during normal operation) is used to isolate the loop output, from the SG-811 phase lock input (which is nothing else than a heavy VCO=voltage controlled oscillator). A few extra parts are also connected to feed a test signal to the VCO, in addition to the loop filter output voltage.
This test port is intended to disturb the PLL just a bit, without causing loss of phase lock, and measure the response. Such work is best done with a dynamic signal analyzer – I’m using a HPAK 3562a, not because it is the latest model, but because that’s what I have around here in my temporary workshop. It had the old CRT replaced by a nice color LCD screen, and it features a very acceptable noise floor, and gain/phases analysis.

The test setup (please excuse the mess, not too much empty bench space around here)
pll loop test - micro-tel sg-811 - adf41020

Now we just need to work through various frequencies and settings, to better understand the characteristics of the system.
To cover all the YIGs and bands of the SG-811 (which might have unknown variations in tuning sensitivity, noise, etc.), frequencies around 2, 6, 10, 12.5 and 17.5 GHz were chosen for the test (exact values can be found in the worksheet, better not to use even values, e.g., 2.0000 GHz, but to exercise the divider circuits – to see if there are any spurs).

At each frequency, magnitude and phase response was collected, examples:
Gain (disregard the unstable response below 10 Hz, just an artifact)
mag_cp0

Phase
phase_cp0

The interesting point is the 0 dB crossing of the gain trace – the unity gain bandwidth. This is determined for each test condition, and then the corresponding phase is obtained from the phase plot. In this example, BW_0dB is about 380 Hz, with about 20 degrees phase. Why is it so important? Simply because we need to keep this phase gap (of the A and B signals) well above 0 degrees, otherwise, the loop will become unstable-oscillate-massive phase noise of the generator will result.

Some call this the phase margin, so do I, although the whole discussion about gain and phase margins is typically centered around open-loop system, whereas we are dealing with a closed loop here. Fair enough.

Now, after some measurements, and number crunching, the results:

Phase vs. BW, at various frequencies
pm vs bw sg-811 pll
-you can see, the phase margin is virtually independent of frequency, and purely a function of bandwidth. So we can limit all further discussion to bandwidth, and don’t need to worry about phase margin separately. It is also clear from this diagram that we should better stay in the 250-300 Hz bandwidth region, for the given filter, to keep the phase margin above 25 degrees, which is a reasonable value.

Now, how to keep the bandwidth stable with all the frequencies and YIGs/SG-811 bands and sensitivities changing? Fortunately, the ADF41020 has a nice build-in function: the charge pump current can be set in 8 steps (0 to 7), from 0.625 to 5 mA (for a 5k1 reference resistor) – and setting the charge pump current (Icp) is not much else than changing the gain of the loop filter. The gain, in turn, will change the 0 dB bandwidth in a fairly linear fashion. Note: typically, the adjustable charge pump current is used to improve locking speed – at wider bandwidth, and mainly, for fixed-frequency applications – but is is also a very useful feature to keep bandwidth stable, for PLL circuits that need to cover a wide range of frequencies, like in the case of the SG-811.

The next result – bandwidth vs. Icp setpoint
sg-811 pll bw vs charge pump current at various frequencies
-looking at this diagram, the bandwidth is not only a function of Icp, but also a function of frequency. For the larger frequencies, the bandwidth is much lower. Some calculations, and it turns out that the product of bandwidth, multiplied with frequency to the power of 0.7 (a bit more than the squareroot) is a good parameter that gives an almost linear vs. Icp (see worksheet, if interested).
adf41020 pll bw phase margin

After all the measurements, things are now pretty clear – if we set the Icp current right, BW can be kept stable, over almost the full range, without any extra parts and switches, and about 300 Hz seems to be a reasonable compromise of PLL speed and stability.

Estimated PLL bandwidth (0 dB), using the Icp current adjustment of the ADF41020
bw vs frq with charge pump current adjustment
At the lowest frequencies (2 GHz range), the BW is found a bit larger than desired, but still, the loop still has 20 degrees margin.

Well, with all the phase margins and uncertainties, is the loop really stable enough? To check this out, what is typically done is to first try a few odd frequencies, at the start, end and in the middle of each band and monitor the VCO control voltage with a scope, for any oscillations or otherwise strange behavior. Then try a few small frequency steps, and see how the loop settles. This all went without any issues.

Still, to be sure, especially close to 2 GHz (increased bandwidth), a test was performed by injecting a 100 mV (nominal) squarewave, 10 Hz, via the test port mentioned above. The loop output spectra showed that this worked, and that the 10 Hz contribution is significant, while still not swamping everything else and driving the loop out of lock right away.

Power spectra with test signal on (upper diagram), and off (lower diagram).
pll power spectra

There are some 60 Hz/harmonic 60 Hz spurs, mainly due to coupling of 60 Hz to the coarse tune line, which is just a plain coax cable that doesn’t provide any good shielding vs. 60 Hz (or 50 Hz, in Europe) interference.

Needless to say, the PLL will not stop working right away when the phase hits 0 deg at the 0 dB point (see above, phase margin vs. bandwidth plot – even at negative phase, measurement was still possible – as long as the amplitude of the test signal is kept small).
There will be signs of instability, and this is what this test reveals. So the frequency was set again to 2.2221 GHz, and the charge pump current Icp increase step by step, from 0 to 5. At 6 and 7, no phase lock could be achieve – fully unstable loop.

Step response (AC component only, square wave, 10 Hz at nominal 100 mV, supplied to test port)
pll step response 2.2221 ghz 100 mV
Icp=0 – this is the most stable condition, phase margin is about 20 degrees. Already at Icp=1, phase margin of about 3 degrees, stability is much compromised/considerably more noise, not only for the step response, but also during the steady portions. At Icp=2 and above, phase margin is negative, still, phase lock is robust (will not re-lock, once lock is lost), and the pulse response suggests to stay away from such regions.

Micro-Tel SG-811 PLL – phase lock achieved!

Thanks to a rainy late afternoon (and evening), some success with getting the SG-811 signal generator phase locked. For external frequency control, the SG-811 needs a coarse tune voltage, to adjust the frequency to within a few MHz of the target. This is done using a DAC8830(=MAX541) 16 bit DAC and OP284 opamp to scale the 0 to 2.5 V of the DAC to 0 to 10 V required for the coarse tune input of the SG-811.

The SG-811 is run at a level of +5 dBm, and a directional coupler is used to get a sample of this signal (about -5 dBm) into a ADF41020 single chip PLL. The remainder of the signal is fed into a EIP 454A microwave counter, which also provides a 10 MHz reference for the PLL.

First, it turned out that the SG-811 uses a different voltage range (-3 to 3 V) for the phase lock input, compared to the Micro-Tel 1295 (0 to 10 V). So the 8904A was used to determine the phase lock input sensitivity (deviation in MHz per Volt). Some existing AVR code (the whole setup is controlled by an ATMega32L) was modified to fit the SG-811 requirements. This code has some nice features, including a self-adjusting coarse tune voltage. This is of great help because the phase lock input of the SG-811 only allows for a few MHz frequency shift, and during warm-up the generator can easily drift out of the lock window, if the coarse tune value is left unadjusted. Obviously, the coarse tune voltage is changed in very small steps, 1 LSB at a time.
Drop me a line if you are interested in more details.

The (temporary) test setup, set to an arbitrary value of 4.5500 GHz.
20140831_223034o

The control circuitry
20140831_223151o
Display shows (second line): Divider values of the PLL, DAC coarse tune value (0 to 65535), band, and phase control voltage (deviation from mid-point in mV, +-100 mV are perfectly fine, if +-50 mV are reached with drift correction activated, the DAC coarse tune will be automatically adjusted to get the phase control voltage back to less than +-10 mV).

Last but not least, also the shift register board, 3x LS164 (for remotely controlling the band switches) has been connected to the AVR micro, and all is functional.

The Microwave PLLs: stabilizing the YIGs

The Micro-Tel SG-811 and 1295 are great units, however, they lack PLL control. Even at their time, in the late 70s, early 80s, government labs required PLL control – and Micro-Tel offered PLL controlled frequency stabilizers for these units. Stabilizers that are now virtually impossible to source (if you have two spare Micro-Tel FS1000, please let me know!).

So I decided to build some very broadband PLL circuits that can handle 2 to 18 GHz, at reasonable frequency resolution. 10 kHz, or 100 kHz resolution seems to be perfectly adequate; mostly, the attenuator calibrator will be used in 2 GHz steps anyway.

Both units have two inputs:

(1) A frequency control input – a voltage controlled input, 0 to 10 V, that sets the frequency roughly, within the given band. Bands are: 2-4, 4-8, 8-12, 12-18 GHz. There is some thermal drift, but preliminary test shows that a 16 bit DAC would be most suitable for this kind of “coarse” frequency control.

(2) A phase lock input. This has a sensitivity of a few MHz per Volt. 0 to 10 V input, for the 1295 – and -3 to 3 V for the SG-811, as it turns out. Accordingly, with the coarse control set to the right value, the phase lock voltage should be somewhere around 3-7 Volts, for the 1295, and close to 0 V for the SG-811.

Now, the tricky part, how to get a phase comparator running, for the 2-18 GHz range? Traditionally, this requires a broadband harmonic generator, locking to a certain harmonic, and so on. All possible, has been done before, but a lot of work to get it working.

There comes the rescue, from Analog Devices: a truely remarkable little thing called ADF41020. It is a full 18 GHz PLL circuit, works with more or less any reference (10 MHz will be used here), and has pretty high input sensitivity, all that is needed are about -10 dBm to drive it over the full band.

After some tricky soldering, in dead-bug style, and some auxilliary circuitry, with 16 bit DAC, reference voltage supply, very clean and stable supplies for the PLL, all the typical loop filters (0.5 KHz bandwidth) – and an ATMega32L – this is the current setup, for the 1295. Believe me, it is working just fine, and even has an auto-track feature, to keep the phase lock voltage mid-range – so it won’t un-lock with drift.

20140825_131843

Upper left hand corner: ADF41020
Lower left hand corner: PLL loop filter
Center: Low noise voltage regulators, reference and DAC
Other parts: ATMega32L board (16 MHz, USB interface), LCD display (just for troubleshooting)