# The best solution, most likely: let the nonlinearities (INL) cancel out

After putting a bit more thought into this, let’s have a look again at the kind of nonlinearity observed for the ADS1211. We only know three points where there will be no error due to non-linearity: the zero point (because that will be covered by the zero point calibration), and the plus (and minus) voltage, at which the gain calibration is carrier out. The gain will be calibrated both for the positive and negative direction, simply by reversing the same calibration voltage, most likely, about 7.x volts, supplied by a LTZ1000.

Again, from the datasheet:

Now, what if we measure not just with one ADC, but with two, of the same kind, and hopefully, with the same non-linearity, but, with the polarity reversed. I.e., because of the fully differential nature, we can measure, simultaneously, the same voltage, both in the positive and negative direction. Doing this adequately should cancel out most of the (integral) nonlinearity. Furthermore, if use two independent references, for the two ADC we will also gain noise margin – because some of the noise in non-correlated and will cancel out – also, we will acquire the same signal independently, and do the averaging digitally! For non-correlated noise, this means about 3 dB gain, about half a bit!

It only means that finally, we will need to put in 8 ADCs to measure two voltages, but, well, who cares – the given application can handle this, specialized equipment, and no relation to the total cost. And, with some luck, it will result in linearity errors of better than 1 ppm, and 7 digits resolution, with pretty fast data rates.

The solid line: non-linearity of ADC1, the dashed line – non-linearity of ADC2, both ADC are running fully synchronized, same control codes to both ADCs. Two digital outputs – and, one output will be fully inversed, directly in the ADC controller (an ATmega32L), to yield the average of the ADC1 reading, and the complementary of ADC2. Sure the difference to 0 V can also be analyzed, to check how far off the individual values are.
The ATmega32L will also do some decimation, from 60 Hz, to maybe 5 Hz or 1 Hz (independent of the mains frequency), and sent the data to the main controlled, via an optoelectronic isolator (the full ADC section design with fully floating digital and analog grounds). 1200 or 2400 baud will be plenty to get the data out. 60 Hz 6 bytes would be 360 bytes per second, about 3600 baud (need to count start and stop bit), but with decimation, we don’t need any fast couplers, etc.

Sure, this is currently an idea, and will need a closer look, but I assume, it will do the trick, at reasonable cost.
If it works out, maybe we go one step back in the final implementation – the ADS1211 has a 4 to 1 MUX, and rather than sampling simultaneously – we might just give up the noise advantage, and sample consecutively, once with positive polarity, and then, via another channel, in inverse polarity. But hey, Texas Instruments will be happy to sell a few more ADCs.

Finally, not sure if it is better to run both ADC from the same 10 MHz clock, or from separate clocks – some of the jitter induced noise might average out only, if the jitter sources are independent. So many, option, but quite easy to find out!

# ADS1211 evaluation: a bit of shielding goes a long way…

Following-up on earlier analysis, the ADC performance observed at small decimation (like 1 s averages, with 60 Hz data rate – 60x decimation) left something to be desired – quite a few bits lost due to mains (and/or other) sinusoidal noise.

Look at 1 hour worth of data (60x decimated; each sample: 1 s worth of data), at higher magnification than before – ticks every 15 minutes:

Obiously, there are some bursts. And these are almost certainly not related to the ADC or anything internal to the circuit. Maybe the power supply, but added quite a few decoupling capacitors…

So, if the noise source is external, a bit of shielding might help – great to have a little metal box (even a steel box) at hand!

Note the 2 BNC cables – rather than one – feeding the test signals from a fully-differential source, to avoid ground loops.

Well, not much to add! Amazing what a little metal box can do!

# Studying the local characteristics of the ADS1211: ADC differential nonlinearity, missing codes

To qualify the ADS1211 for the given application, or at least, to gain some confidence in it, a test – not the for overall non-linearity (i.e., non-linearity over the full range, aka integral nonlinearity INL), but for the more detailled view at the ADC’s precision.

Local deviation of an ADC from linearity are called differential linearity, and this can be some slight deviation, or can go so far that there are even “missing codes”. A missing code is caused by a local non-linearity that is larger than 1 LSB, to the ADC will jump 2 steps, even if the voltage is only increased by 1 LSB equivalent.

First, the test setup: still the ADS1211, running at 4 MHz, 16 turbo mode, 60 Hz data rate. Connected by fully-differential coax to a (floating) source, an HPAK 8904A signal generator. This is programmed for a 5 DV output, with 20 mVpp (intentional) sine ripple, 13 Hz. The selection of the frequency is rather critical, don’t let it be anywhere close to a subharmonic or harmonic of the data rate!
The HPAK 8904A is actually really great for this purpose, you can add and mix any signals, up to 4 channels, and modulations, as desired, into one channel!

Alternatively, you could feed DC-biased noise, but these noise signals can be troublesome, and you never now what to expected in terms of amplitude, flatness, etc, unless you have really specialized gear.

Having everything set up, several hours of data were collected. Virtually no drift, so the DC component-the average ADC code (nearest integer) was subtracted from the data, and the results analyzed.

Full data, +-2000 counts is more or less +-10 mV (20 mVpp), as expected. 1 LSB is about 4 µV. There is dot for every count, even if no sample was recorded, at the given count (then, the dot is at 0 samples…).

The probability density function (PDF) corresponds to that of a sine function. That’s a good start.
Some key observations – there seem to be 3 “populations” of sample counts – codes that are “0”, i.e., missing codes; codes that have counts that are somewhat in-between (the majority), and double-counting codes. This needs some more investigation.

Taking all these data, and the know PDF of sine (of the form, 1/(x*(1-x), “bathtub curve”), the PDF was fit to the data, using least squares.

Green line shows the fit-this makes sense, and the residuals were calculated.

We are only interested in the center part, where the errors due to drift are minimal. A close up:

We can cleary see a pattern: DxMMxxMMxxMMxxMMDxMMxxMMxxMMxxMMD…
D – double code, M – missing, x – intermediate.

What seems dramatic, it’s acutally not. There aren’t any deviations more than +-1 LSB, and there will be noise and averaging anyway, to get beyond even 22 bit resolution.

# Noise: external and internal

A quick – 9 hour test – of the ADS1211: at 60 Hz data rate, 16x turbo mode. About 2 million samples.

According to the datasheet, every sample will yield about 22 bits noise free data, according to the datasheet (red circle shows setting used):

That’s what has been obtained.

Clearly visible, higher density of codes at the left and right end. Really suspicious – almost certainly, nothing else than a bit of mains feed-through, about 175 µVrms. Seems we get >20 bits, more or less, otherwise we would not be able to see the distribution (note that some counts have a positive deviation – due to non-linearity!).
But all this, with some 60 Hz noise on top…
Assuming that this noise is constant, it can be eliminated either by futher digital filtering, or by averaging/further decimation of the data, which will be done anyway. As a rule of thumb, decimation by half will give an extra 0.5 bit of data, for random noise – and a bit more for constant 60 Hz.

Here, a quick look at the decimated data (note that the sample axis ticks correspond to 2 hours time intervals):

In these diagrams, “full scale” corresponds to 20 V – the current configuration can hande up to 60 V differential signal, at 1 LSB equal 4 µV. So there is still room for improvement of resolution, like 1 LSB equal 2 µV – but this only provides useful data, if we can get noise down well below 2 µV, which will be tough anyway.

Also, quick statistical analysis, of the 10 s average – 600 sample average data:

Standard deviation, 0.71 LSB equals 0.71 LSB RMS noise, equals 3 µV. Quite reasonable!
Still visible are the two maxima of the distribution, due to the mains noise.

Comparing to a random-noise based decimation-improved resolution (noise free bits), it seems that the converter is yielding about 20 noise free bits, at 60 Hz data rate. Not quite the 22 bits mentioned in the datasheet. This is not surprising, the last 2 bits, at the fast rate, we will only be able to get this with a better, ultra low noise reference, a low-noise bias supply, and low noise analog power supply (currently using the build-in reference, and build-in bias supply, and 5 V supply from USB bus…). But fair enough, about 24 noise free bits (7.5 digits!), at 10 s averaging, and 9 hours zero point drift of less than 0.4 ppm, this might already be good enough.

# Probability density function – calibrating the ADC: test run with the ADS1211

To further advance the ultra-linear ADC project, a little test setup has been deviced. Naturally, the final setup will require strict low noise construction, with only the best low-drift parts in the analog chain, and so on. At the moment, I just need to get to code running and tested to some kind of precision, therefore, a makeshift assembly will be good enough.

For the ADC, an Texas Instruments ADS1211 24-bit sigma-delta ADC, with a 4-channel MUX has been selected, simply because I have it around, and it has a good accuaracy to start with, about 15 ppm non-linearity, and no missing codes up to 22 bits.

A diagram from the datasheet, the non-linearity looks fairly well behaved – my confidence in hitting the 1 ppm mark is growing!

The ADS1211 is really a great part, for what it is, and for the price (about USD 25 each), and I have been using it a for a major projects in the past, 3 or 4 years ago.

The build in 2.5 V reference is not the most stable and quiet, but will do for now.
Input is configured for +-10 V bipolar, using 3.9 k-1 k Ubias resistors.
Clock frequency is 4 MHz, a sub-harmonic of the 16 MHz of the ATmega32L controlling it (again, the famouse JY-MCU board).

A simple trick for soldering SOIC parts to a 0.1″ pitch prototype board: just place the part on the table, upside down, and bend down, with a screwdriver, every second pin. It will be working just great, and no issue at all with soldering it, even if you don’t have good tools at hand.
No need at all for any special SMD boards, etc., just a waste of time, from my point of view.

Now, for a quick test, connected a sinewave (10 Hz), and sampled at a few Hz.
More cables than actual parts.

With the sinewave at the input, and constantly sampled, the ADC output should resemble the sine function – however, we don’t want to analyze each measurement individually, but will collect massive amounts of data, and put them into bins – looking at the sine function, not all output values have the same probability – the values at the extremes will be more frequent, because there, the sine function is more flat than close to zero. No need to give the exact maths here, just a little diagram:

In the final application, we will cut-off the outer parts, and just use the middle section. For today, that’s the result of a quick test:

Well, quite satisfactory for a start – next step will be to figure out the details (sampling rates, data transfer protocols to avoid lost samples, fast code to sort large number of samples; also, need to find out how the local varation of nonlinearity related to the larger-scale variation – by sampling for several hours…). Will all be done, step by step.
Another idea is to measure the frequency/period of the sine test signal, and using the zero-crossing as a sync pulse, to time-stamp/calculate the acutal voltage at a given time, and correlate by a least-square of similar algorithm with the ADC digital output.