Tag Archives: fractional N

Fractional-N PLL for the Micro-Tel 1295 receiver: some progress, more bandwidth, two extra capacitors, and a cut trace for the SG-811

Step 1 – Programming of the ADF4157, no big issue – fortunately, all well documented in the datasheet. The 1.25 MHz phase detector frequency selected will allow tuning in integer-only (no fractional divider) 10 MHz steps (considering the :8 ADF5002 prescaler).

One sigificant difference to the ADF41020 – the ADF4157 uses 16 steps for the charge current control (0=0.31 mA to 15=5.0 mA).

Step 2 – Checking for lock at various frequencies – in particular, at the low frequencies – the thing is running really at the low edge, 250 MHz input for the ADF4157. However, despite all concerns, no issues, prescaler and PLL are working well even at the low frequency. Quite a bit of noise! Not out of focus…
1295 noisy signal

The PLL is locking fine, but still, significant noise in the loop, and also visible in the 1295 scope display, with a very clean signal supplied to the receiver… bit of a mystery. When the PLL is disengaged, and the 1295 manually tuned – no noise, just some slow drift.

Step 3 – Increased loop bandwidth to about 8 kHz, even more noise – seems to PLL is working against a noisy FM-modulated source…. a mystery. Checked all cables, nothing is changing when I move them around.

Step 4 – Some probing inside of the 1295, and review of the signal path for the PLL tune and coarse tune voltages. And, big surprise – there is a relais (K1) on the YIG diver board, and this disengages a low-pass in the coarse tune voltage line – it is a 499k/22 µF RC, several seconds time constant.

See the red-framed area:
micro-tel 1295 A3B9 YIG driver loop damping

Tackling this through a lowpass in the coarse tune feed line (from the coarse tune DAC) didn’t change a thing – the noise is getting into the YIG driver from instrument-internal sources, or partly from the opamp (U5, LM308) itself, when it is left running at full bandwidth. As a side comment, note the power amplifier – it is a LH0021CK 1 Amp opamp, in a very uncommon 8 lead TO-3 package. Hope this will never fail.

Usually, I don’t want to modify test equipment of this nature, because there is nothing worse than badly tampered high grade test equipment. All conviction aside, 2 X7R capacitors, 100 n each, were soldered in parallel to the R38 resistor, so there will be some bandwidth limitation of the YIG driver, even with the K1 relais open.
micro-tel A3B9 YIG driver board - modified

With these in place – the noise issue is gone.
1295 clean signal

Now, triggered by this discovery – the SG-811 uses a very similar YIG driver board, which also has a low pass engaged, in the CW mode – however, not in the remotely controlled CW mode, with externally settable frequency… easy enough, just one of the logic traces cut, and now the filter stays in – don’t plan on sweeping it with a fast acting PLL anyway.

Back to the fractional-N loop: after some tweaking, the current loop response seems quite satisfactory. Set at 3 kHz for now, with plenty of adjustment margin, by using the 16-step charge pump current setting of the ADF4157. Getting 45 degrees phase margin (closed loop) at 3 kHz – therefore, should also work at higher bandwidth. Will see if this is necessary.

PLL gain
1295 fractional-n loop mag

PLL phase
1295 fractional-n loop phase

Fractional-N PLL for the Micro-Tel 1295: ADF4157/ADF5002

After spending most of the day at the beach, some more experimentation – with a fractional-N approach. Two little chips were around from another project, why not give it a try:

(1) The Analog Devices ADF4157, 6 GHz, 25 bit fixed modulus fractional-N PLL – this part is really great, for many purposes. It’s more or less pure magic what these folks at Analog do and achieve.

(2) To make it work up to 18 GHz, a prescaler is needed. Well, unfortunatly, I only have a :8 prescaler (ADF5002) around – this will give 0.25 to 2.25 GHz, for the 2 to 18 GHz input. Not quite ideal, because at 2 GHz it’s getting really into low frequencies for the ADF4157, and the output power of the ADF5002, which is a more-than-sufficient -5 dBm in the 4 to 18 GHz, range, but dropping off to only about -10 dBm at 2 GHz. At the same time, RF input sensitivity of the ADF4157 drops considerably for input frequencies below 0.5 GHz… we will see.

Some calculations:
With a 10 MHz reference clock, and the phase detector frequency set to 1.25 MHz (reference divider=8), this will result in 10 MHz steps, with 2^25 spacings in between. This gives about 0.298 Hz resolution. And moreover, with this setting, 10 MHz steps are possible, with no fractional-N divisor (which can always lead so some rather unpredictable fractional-N spurs).

The circuit – there is no big secret to it, a 5k1 reference resistor to set the charge pump current to 5 mA, and a few 6k8 resistors (0805 SMD) to make the chip compatible to a 5 V digital world. Two SMA connectors – one for the signal, and one for the 10 MHz reference. All wiring is done with 0.08 mm tinned copper wire… hope you have a steady hand. With a drop of epoxy glue, everything is held in place and well-protected.



Tests will follow – currently the loop bandwidth tests are running for the 1295, with the ADF41020 PLL.