Tag Archives: loop filter

Micro-Tel MSR-904A Microwave Receiver: phase lock test, YIG driver bandwidth modification

Some final parts added to the MSR-904A digital interface/PLL: the actual PLL circuit (frontend), an Analog Devices ADF4157 fractional-N PLL, together with an ADF5002 8:1 prescaler. The phase detector is set at 1.25 MHz, to allow 10 MHz integer-only steps. Some experimentation with other phase detector frequencies might follow later.

Here – the schematic of the PLL frontend. The circit is wired point-to-point, sure enough, with VERY short wires, soldered using a microscoped – hope you have a steady hand. After a quick test (using the MUX output of the ADF4157), the wires and the very tiny ADF gadgets, all sealed with a few drops of epoxy.

msr pll adf5002 adf4157 schematic

On the main board, the PLL loop filter. Build around the remaining half of the already installed OPA2703 (other half used for the DAC output buffer).

msr pll loop filter

With all these parts now put together, to do some basic tests on the PLL – a Gigatronics 605 Microwave Synthesizer was connected to the MSR-904A input, and the LO sample output of the MSR-904A connected to PLL. A sample of the “LO sample” taken by a broadband -10 dB coupler is used to monitor the frequency, using an EIP 545A. The 10 MHz reference output of the EIP is used as the ADF4157 reference.

msr pll phase lock test setup
msr pll test setup 2

The MSR-904A down-converts the signal to a first 250 MHz IF (by fundamental LO), the 250 MHz IF is then mixed with 410 MHz (this can be locked to a 5 MHz signal – not locked at the moment, but the signal is very clean and stable anyway).

The 160 MHz 2nd IF is available at the rear panel, and connected to a R820T RTL SDR. This is a very handy method to monitor noise, and do some basic adjustments on the PLL. Using headphones – and the human ear as a phase noise meter… more quantitative analysis to follow.

Here, the transition from manually controlled CW mode, to PLL controlled mode.
msr-904a locked at 7250 mhz lo

A close-up:
msr-904a locked at 7250 mhz lo 2

For these tests, the LO was locked at 7.25 GHz, receiving a signal at 7.0 GHz (SDR offset set to about 160 MHz).

Note – same as for the Micro-Tel 1295, and the SG-811 – the YIG driver has a bandwidth limit (by a 100 uF Tantalum capacitor – and a 499 k resistor!) that is controlled by a reed relais on the YIG driver. This doesn’t allow low phase noise operation, even with the best PLL. Well, 100 uF is a bit too much. Therefore, a 100 n capacitor was added – this is enough to suppress most of the noise of the YIG driver stage, and still the circuit remains fast enough for full band sweeps at moderate scan rates. Might modify this later, by adding a bit of logic that adds the 100 n capacitor only when the external frequency control is active, but disconnects it during full band sweep, etc.
msr-904a YIG driver board

PLL frequency response measurement: a ‘not so fancy’ approach, for every lab

Measuring gain and phase shift of some decice doesn’t seem like a big deal, but still, how is it acutally done? Do you need fancy equipment? Or is it something of value for all designers of PLLs that don’t just want to rely on trial and error?

The answer – it’s actually fairly easy, and can be done in any workshop that has these items around:

(1) A simple function generator (sine), that can deliver frequencies around the band width of the PLL you are working with. Output level should be adjustable, coarse adjustment (pot) is enough. You will need about 1 Vpp max for most practical cases.

(2) A resistor, should be a considerably lower value than input impedance of the VCO. Typical VCOs might have several 10s of kOhm input impedance. Otherwise, put a unity gain opamp (e.g., OPA184) in between the resistor and the VCO tune input.

(3) A resistor, and some capacitors (depends a bit on the bandwidth), for general purposes 10-100 kHz, a parallel configuration of a 100n and 2.2 µF cap is just fine. In series with a resistor, a few kOhms. This network is used to feed a little bit of disturbance to the VCO, to see how the loop reacts to it… the whole purpose of this exercise.

(4) Make sure that the loop filter has low output impedance (opamp output). If your circuit uses a passive network as a loop filter, put in an opamp (unity gain) to provide a low output impedance.

(5) A scope, any type will do, best take one with a X-Y input.

Quick scheme:
pll gain phase measurement diagram

To perform the acutal measurements, the setup is powered up, and phase lock established by adequately setting the dividers, as commonly done.
The signals (X: drive=input to the VCO, Y: response=output of the loop filter) are connected to the scope. Set the scope to XY mode, AC coupled input, and SAME scale (V/div) on X and Y.

Next, set the signal gen to a frequency around the range of the expected 0 dB bandwidth (unity-gain bandwidth), and adjust the amplitude to a reasonable value (making sure that the PLL stays perfectly locked!). Amplitude should be several times larger than the background, this will make the measurements easier, and more accurate. If you have a spectrum analyzer, you can check for FM modulation. On the Micro-Tel 1295, which has a small ‘spectrum scan’ scope display, it looks like this:
1295 fm modulated signal during gain-phase test

On the X-Y scope display, depending on where you are with the frequency, it should show the shape of an ellipse, somewhat tilted – examples of the pattern (“Lissajous pattern”) below.

Frequency lower than 0 dB bandwidth – in other words, the loop has positive gain, therefore, Y amplitude (output) will be larger than X (input)
pll gain phase measurement - positive gain (frequency below BW)

Frequency higher than 0 dB bandwidth – in other words, the loop has negative gain, therefore, Y amplitude (output) will be smaller than X (input)
pll gain phase measurement - negative gain (frequency above BW)

And finally, same signal amplitude in X and Y direction.
pll gain phase measurement - 0 dB condition

Sure enough, you don’t need to use the X-Y mode, and circular patterns – any two channel representation of the signals will do, as long as their amplitude is measured, and the frequency identified, at which X and Y have equal amplitude (on the X-Y screen, also check the graticule, because the 45 degrees angle is not so easy to judge accurately). That’s the unity gain (0 dB bandwidth) frequency we are looking for. With little effort, the frequency can be measured to about 10 Hz.
The X-Y method has the big advantage that it relies on the full signal, not just certain points, and triggering a PLL signal with a lot of noise can be an issue.

Try to keep the amplitude stable over the range of frequencies measured – by adjusting the signal gen.

Ideally, the 0 dB bandwidth is measure at various frequencies over the full band of your VCO, because the bandwidth can change with tuning sensitivity, etc., of the VCO.

The 0 dB bandwidth is not the only information that can be extracted – also the phase shift is easily accessible. Just measure, at the unity gain frequency, or any other frequency of interest for you, the length of the black and red lines:
pll gain phase measurement - 0 dB condition - phase determination

The phase angle is then calculated by: divide length of red line, by length of black line, in this case, 4.6/6.9 units. Then apply the inverse sin function, to get the phase angle, sin^-1(4.6/6.9)=41.8 degrees. The 0 dB frequency, in this case, was 330 Hz.

A quick comparison with the data acquired using a more sophisticated methods, a HPAK 3562A Dynamic Signal Analyzer.

Gain: 0 dB at 329 Hz – that’s close!
pll test result - gain

Phase: 38.7 degrees – fair enough.
pll test result - phase

A proper PLL setup should provide at least 20 degrees of phase shift (note that this is not the so-called phase margin, which is a property of an open loop). Closer to 0 degrees, and the loop will remain stable, but a lot of noise (phase noise) and osciallation, finally, occasional loss of lock will be the result.

It’s also a good idea to check that the gain function drops off nicely – there are certain cases, where mulitiple 0 dB points exist – you need to look for the 0 dB point at the highest frequency.

Any questions, or if you need something measured, let me know.

PLL measurements continued… ADF41020 locking the Micro-Tel 1295

With the work on the Micro-Tel SG-811 generator PLL mostly completed, some trials with the Micro-Tel 1295 receiver – this instrument has similar YIGs fitted, just needs to be tuned 30 MHz above the actual frequency tuned, because the 1295 is running on a 30 MHz IF (all diagrams have tuned frequencies, not LO frequencies).

After some crude analysis of the schematics, the 1295 seems to be able to handle a bit more PLL bandwidth – so the target set more in the 500 Hz to 1 kHz region, and some calculations were carried out with the ADIsimPLL program, to determine the rough capacitor and resistor values – otherwise, the loop filter is the same as for the SG-811 PLL, also using an OPA284 opamp.

Otherwise, pretty much comparable results (earlier post related to the SG-811), for example (17.8141 GHz tuned/17.8171 GHz LO frequency, Icp setting 6):

Gain (disregard 1 to 10 Hz)
micro-tel 1295 17814100 kHz cpc6 gain

Phase
micro-tel 1295 17814100 kHz cpc6 phase

After quite a few of these measurement (doesn’t actually take too long), the results.
adf41020 pll bw phase margin 1295

Phase margin vs. bandwidth
pm vs bw adf41020 micro-tel 1295

Bandwidth vs. charge pump current Icp setting, at various frequencies
bw vs icp at various frq adf41020 micr-tel 1295 pll

Again, a bandwidth frequency^0.7 product could be used to get the numbers down to two parameters – slope and intercept of the bandwidth*frequency^0.7 vs. Icp setting curve.
Finally, suitable Icp settings for a 600 Hz target BW:
bw vs frq adf41020 micro-tel 1295 with Icp adjustment

The result seems quite satisfactory, pretty much constant 600 Hz BW can be achieved over the full 2 to 18 Ghz range, at about 47 degrees phase margin. This should allow for stable operation. No locking issues were observed at any of the frequencies, even with full Icp current.

Fractional-N PLL for the Micro-Tel 1295: ADF4157/ADF5002

After spending most of the day at the beach, some more experimentation – with a fractional-N approach. Two little chips were around from another project, why not give it a try:

(1) The Analog Devices ADF4157, 6 GHz, 25 bit fixed modulus fractional-N PLL – this part is really great, for many purposes. It’s more or less pure magic what these folks at Analog do and achieve.

(2) To make it work up to 18 GHz, a prescaler is needed. Well, unfortunatly, I only have a :8 prescaler (ADF5002) around – this will give 0.25 to 2.25 GHz, for the 2 to 18 GHz input. Not quite ideal, because at 2 GHz it’s getting really into low frequencies for the ADF4157, and the output power of the ADF5002, which is a more-than-sufficient -5 dBm in the 4 to 18 GHz, range, but dropping off to only about -10 dBm at 2 GHz. At the same time, RF input sensitivity of the ADF4157 drops considerably for input frequencies below 0.5 GHz… we will see.

Some calculations:
With a 10 MHz reference clock, and the phase detector frequency set to 1.25 MHz (reference divider=8), this will result in 10 MHz steps, with 2^25 spacings in between. This gives about 0.298 Hz resolution. And moreover, with this setting, 10 MHz steps are possible, with no fractional-N divisor (which can always lead so some rather unpredictable fractional-N spurs).

The circuit – there is no big secret to it, a 5k1 reference resistor to set the charge pump current to 5 mA, and a few 6k8 resistors (0805 SMD) to make the chip compatible to a 5 V digital world. Two SMA connectors – one for the signal, and one for the 10 MHz reference. All wiring is done with 0.08 mm tinned copper wire… hope you have a steady hand. With a drop of epoxy glue, everything is held in place and well-protected.

20140903_223309

20140903_223233

Tests will follow – currently the loop bandwidth tests are running for the 1295, with the ADF41020 PLL.

Noise and spurs, ADF41020/Micro-Tel SG-811 PLL

After getting things worked out with the loop filter, some quick check for spurious responses. To do such analysis near the noise level, a FFT/dynamic signal analyzer can be used, but I find it somewhat troublesome, and rather use a swept frequency analyzer for any such work that goes beyond 1 kHz. Below 1 kHz, the FFT is hard to beat. One of the few exemptions is the HPAK 3585A spectrum analyzer, which covers from about DC to 40 MHz, and has resolution bandwidth filters of down to 3 Hz (discrete hardware, not software filters), with baseline at -135 dBm, or lower.

The 3585A doing its thing…
20140902_214758a

The results – 1 to 500 Hz
348_00_0001 to 05
Mainly 60 Hz harmonics – well, will need to keep the cables short (especially the coarse tune cables) and everything far away from mains transformers.

10 Hz to 5 kHz
348_00_001 to 5
Signal at 1 kHz is about -70 dBm, not much. No spurs.

5 to 30 kHz
348_00_5 to 30
Two unexpected spurs – 1st: 19.986 – this is an artifact of the 3585A. 2nd: 18766, this seems unreleated to the PLL (doesn’t change with frequency or divider settings), maybe some switchmode supply stray. Well, down below -100 dBm.

25 kHz (with some 60 Hz harmonic sidebands, -115 dBm) – reference spur, about -93 dBm.
25 khz spur detail

All in all, with some refinement of the software, and a bit of mechanical work to get this all mounted into a nice case, the setup should work find and provide great service.
Sure enough, some direct phase noise measurements on the SG-811 output will eventually follow, once the opportunity is right and the equipment at hand.