Tag Archives: PLL

USB RTL SDR 28.8 MHz Reference: dividers, PLL, success

With the 28.8 MHz VCO design established, all we need to move this project on are divers for the 28.8 MHz (VCO) and 10 MHz (Reference) signals, a slow-acting PLL, and some auxilliary circuitry to feed the 28.8 MHz back to the RTL SDR.

The 28.8 MHz and 10 MHz signals are AC coupled with about 1 kHz input impedance, this is quite common for any 10 MHz reference signal input (used for various kinds of test equipment). These signals are then amplified/limited by unbuffered inverters, 74HCU04. This is a very cost-effective and easy solution, the HCU04 has push-pull outputs, and input clamping diodes. Still, some clamp diodes have been added for the 10 MHz input, just in case.

28.8 mhz divider chain schematic

Looking at 28800 kHz, and 10000 kHz, 400 kHz is the largest common denominator. Accordingly, we need :72, and :25 division factors.

Division of the 10 MHz down to 400 kHz is accomplished by two 74LS90, but you can use other TTL decade dividers, these were just the circuits I had in stock.
28.8 to 400, a bit more tricky, first, divided by 8, using a 74LS293, and another LS293 that has two diodes, acting as an “OR”, to reset the counter when count 9 is reached.

Both 400 kHz signals are then compared use a flip-flop phase comparator, conveniently packaged in a 4046 PLL. For convenience, and to avoid digital noise on the 12 V rail powering the VCO, the 4046 is powered only from 5 V. This somehow limits the tuning output range, from close to 0 V, to about 3.1 V.

The loop filter is very slow acting, tens of seconds, because the objective of this PLL is to correct long-term drift of the 28.8 MHz reference, introduced by temperature, Xtal drift, etc., but otherwise not to impact its noise and oscillation characteristics.

28.8 mhz pll and loop filter schematic

The VCO (see earlier post, VCO design) uses a fixed capacitor to set the tuning offset, this was changed to 4.4 pF, and finally to 2.2 pF, to properly center the tuning voltage (V_tune, output of the PLL loop filter buffer) within the 4046 output range, at roughly 1.7 V.
Extentensive testing was carried out the ensure that the VCO starts up properly, even if extreme V_tune voltages are applied; as the 28.8 MHz Xtals used in the USB RTL SDR devices may vary, you will need to check the required tuning range and pullability of the Xtal. Some Xtals oscillators will stop oscillating, if you pull to frequency up or down too much, which might happen during PLL start-up. This can lead to an undesirable lock-up condition.

Here are the tuning characteristics, for 2p2, and 4p4 pF VCO capacitor values.

28.8 mhz tuning

This is the divider and PLL board. Sure it would be much nicer to have everything completely separated, in shielded cans, etc., but I did not go to such effort. Later testing will reveal if it has any bad consequences for the 28.8 MHz phase noise, but so far, I don’t see much noise – will do a more in-depth comparison later.

28.8 mhz pll boad

Oscillator Driver/PLL: tuning fork oscillator

Recently, a “very special” circuit had to be designed – a driver for a mechanical oscillator. The objective – to find the natural frequency of such oscillators, to a very high degree of precision, and at very small amplitudes, in the µm range.
Measurement of the frequency is easily done by a frequency counter – what is needed is a circuit that keeps the oscillator going at a constant amplitude.

The oscillator (a mechanical tuning fork, metal tube) carries a small magnet that can be used, together with a stationary coil, to make is oscillate and sustain the oscillation.
The movement of the tuning fork is sensed by a light gate – an IR emitter diode, and a photodiode.

The oscillator is running at a few 100 Hz, in a very well thermostated environment.

First part, the photodiode amplifier, and signal conditioning circuits.
osc pickup and amp

The second part, the PLL (a classic 4046), and some auxiliary circuitry to provide monitor outputs.
osc pll-vco
For operation at other frequencies – adjust the VCO timing capacitor, or use an external VCO.

The coil driver – and monitor driver, this is a very low power systems, a few milliamps are plenty for the coil.
osc coil driver

Micro-Tel MSR-904A Microwave Receiver: reducing phase noise – phase detector frequency

Like with most PLL build, there a quite a few things that can go wrong – the result: a lot of phase noise. For the current setup, all precautions had been taken to avoid bad surprises – low noise supplies, well-proven loop filter amplifier, low noise DAC, adequate cables. And, phase lock was quickly achieved (see last post).
For more detailed analysis, both the 160 MHz and the 21.4 MHz IF signals of the MSR-904A are fed to analyzers. For the 160 MHz, to a RTL SDR stick, just for the rough picture, and the 21.4 MHz, to a 3585A analyzer. The 3585A has very low noise, ideally suited to look at phase noise, except if you are working the ultra low noise segment.

Initial finding – phase noise is down at about 60 dBc at >10 kHz offset, dropping off as expected, but the close-in noise is really bad. Close in noise often related to the phase detector, or the reference. Substituting the 10 MHz reference from the EIP545A by a really low noise HP 10 MHz OCXO didn’t change much. So to high noise level must be connected to phase detector.

With the detector set to 1.25 MHz (:8 reference divider), there we can gain quite a few dB of noise supression, by increasing the detector frequency (within limits, doubling the detector frequency lowers the associated noise contribution by about 3 dB). And, even more, we can check out the reference doubler, which is a build-in feature of the ADF4157. With the doubler in use, it needs to be ensured that the duty cycle of the reference is close to 50%, but this is ensured by the OCXO anyway.

The ADF4157 can handle phase detector frequencies of up to 32 MHz, no issue at all with 20 MHz. The only downside – more fractional-N spurs – channel spacing for integer only dividers is now 160 MHz, rather than 10 MHz….

msr pll phase noise

msr pll phase noise averaged

Red and green traces – you can see, the PLL is completely detector noise saturated within the bandwidth.

Other traces – all with a phase detector frequency of 20 MHz – and at different charge pump currents (CPC). A CPC of 15 corresponds to a 5 mA current. This has direct impact on the phase loop cut-off frequency. There is some peaking, at 2 kHz (dark blue trace, CPC 1), and at about 7 kHz, light blue trace, CPC 10.

Comparing the yellow and magenta traces – these differ by the 10 MHz reference signal source only (yellow uses an HP 10811 OXCO, magenta uses the EIP 545A build-in reference which is pretty stable, but rather noisy). In the curent setup, both references yield very similar results – accordingly, the noise within the PLL bandwidth is dominated by the PLL cirucit itself, and the phase detector, not the reference source.

There are some mains-related spurs at 60 and 180 Hz, but these might just be due to the temporary cabling and lack of a proper case. The circuit is fully exposed, tranformers closeby, etc. For the final setup, all cables will need to be as short as possible, especially for the pretune voltage (which is about 2 MHz per Volt – 2 kHz noise for 1 mV!).

Credits go to KE5FX for the great PN.EXE phase noise measurement tool, invaluable for any such work!

Micro-Tel MSR-904A Microwave Receiver: phase lock test, YIG driver bandwidth modification

Some final parts added to the MSR-904A digital interface/PLL: the actual PLL circuit (frontend), an Analog Devices ADF4157 fractional-N PLL, together with an ADF5002 8:1 prescaler. The phase detector is set at 1.25 MHz, to allow 10 MHz integer-only steps. Some experimentation with other phase detector frequencies might follow later.

Here – the schematic of the PLL frontend. The circit is wired point-to-point, sure enough, with VERY short wires, soldered using a microscoped – hope you have a steady hand. After a quick test (using the MUX output of the ADF4157), the wires and the very tiny ADF gadgets, all sealed with a few drops of epoxy.

msr pll adf5002 adf4157 schematic

On the main board, the PLL loop filter. Build around the remaining half of the already installed OPA2703 (other half used for the DAC output buffer).

msr pll loop filter

With all these parts now put together, to do some basic tests on the PLL – a Gigatronics 605 Microwave Synthesizer was connected to the MSR-904A input, and the LO sample output of the MSR-904A connected to PLL. A sample of the “LO sample” taken by a broadband -10 dB coupler is used to monitor the frequency, using an EIP 545A. The 10 MHz reference output of the EIP is used as the ADF4157 reference.

msr pll phase lock test setup
msr pll test setup 2

The MSR-904A down-converts the signal to a first 250 MHz IF (by fundamental LO), the 250 MHz IF is then mixed with 410 MHz (this can be locked to a 5 MHz signal – not locked at the moment, but the signal is very clean and stable anyway).

The 160 MHz 2nd IF is available at the rear panel, and connected to a R820T RTL SDR. This is a very handy method to monitor noise, and do some basic adjustments on the PLL. Using headphones – and the human ear as a phase noise meter… more quantitative analysis to follow.

Here, the transition from manually controlled CW mode, to PLL controlled mode.
msr-904a locked at 7250 mhz lo

A close-up:
msr-904a locked at 7250 mhz lo 2

For these tests, the LO was locked at 7.25 GHz, receiving a signal at 7.0 GHz (SDR offset set to about 160 MHz).

Note – same as for the Micro-Tel 1295, and the SG-811 – the YIG driver has a bandwidth limit (by a 100 uF Tantalum capacitor – and a 499 k resistor!) that is controlled by a reed relais on the YIG driver. This doesn’t allow low phase noise operation, even with the best PLL. Well, 100 uF is a bit too much. Therefore, a 100 n capacitor was added – this is enough to suppress most of the noise of the YIG driver stage, and still the circuit remains fast enough for full band sweeps at moderate scan rates. Might modify this later, by adding a bit of logic that adds the 100 n capacitor only when the external frequency control is active, but disconnects it during full band sweep, etc.
msr-904a YIG driver board

PLL characterization – final results for the Micro-Tel SG-811 and Micro-Tel 1295 circuits

After some experimentation, measurements, etc. – as described before, time to wrap it up.

The PLL loop filter output is now connected to the phase lock input (the additional 1 k/100 n low pass in the earlier schematic has been omitted), with a 330 Ohm resistor in series. This will remain in the circuit, because it’s handy to characterize the loop, and to provide a bit of protection for the opamp output, in case something goes wrong, to give it a chance to survive.

With the charge pump current adjustments now implemented in the software, that’s the result, all pretty stable and constant over the full range.

The SG-811 signal source
micro-tel sg-811 pll bandwith vs frequency

The 1295 receiver
micro-tel 1295 pll bandwidth vs frequency

Micro-Tel SG-811 PLL: frequency response
sg-811 final gain

sg-811 final phase

Micro-Tel 1295: frequency response
1295 pll final gain

1295 pll final phase

PLL frequency response measurement: a ‘not so fancy’ approach, for every lab

Measuring gain and phase shift of some decice doesn’t seem like a big deal, but still, how is it acutally done? Do you need fancy equipment? Or is it something of value for all designers of PLLs that don’t just want to rely on trial and error?

The answer – it’s actually fairly easy, and can be done in any workshop that has these items around:

(1) A simple function generator (sine), that can deliver frequencies around the band width of the PLL you are working with. Output level should be adjustable, coarse adjustment (pot) is enough. You will need about 1 Vpp max for most practical cases.

(2) A resistor, should be a considerably lower value than input impedance of the VCO. Typical VCOs might have several 10s of kOhm input impedance. Otherwise, put a unity gain opamp (e.g., OPA184) in between the resistor and the VCO tune input.

(3) A resistor, and some capacitors (depends a bit on the bandwidth), for general purposes 10-100 kHz, a parallel configuration of a 100n and 2.2 µF cap is just fine. In series with a resistor, a few kOhms. This network is used to feed a little bit of disturbance to the VCO, to see how the loop reacts to it… the whole purpose of this exercise.

(4) Make sure that the loop filter has low output impedance (opamp output). If your circuit uses a passive network as a loop filter, put in an opamp (unity gain) to provide a low output impedance.

(5) A scope, any type will do, best take one with a X-Y input.

Quick scheme:
pll gain phase measurement diagram

To perform the acutal measurements, the setup is powered up, and phase lock established by adequately setting the dividers, as commonly done.
The signals (X: drive=input to the VCO, Y: response=output of the loop filter) are connected to the scope. Set the scope to XY mode, AC coupled input, and SAME scale (V/div) on X and Y.

Next, set the signal gen to a frequency around the range of the expected 0 dB bandwidth (unity-gain bandwidth), and adjust the amplitude to a reasonable value (making sure that the PLL stays perfectly locked!). Amplitude should be several times larger than the background, this will make the measurements easier, and more accurate. If you have a spectrum analyzer, you can check for FM modulation. On the Micro-Tel 1295, which has a small ‘spectrum scan’ scope display, it looks like this:
1295 fm modulated signal during gain-phase test

On the X-Y scope display, depending on where you are with the frequency, it should show the shape of an ellipse, somewhat tilted – examples of the pattern (“Lissajous pattern”) below.

Frequency lower than 0 dB bandwidth – in other words, the loop has positive gain, therefore, Y amplitude (output) will be larger than X (input)
pll gain phase measurement - positive gain (frequency below BW)

Frequency higher than 0 dB bandwidth – in other words, the loop has negative gain, therefore, Y amplitude (output) will be smaller than X (input)
pll gain phase measurement - negative gain (frequency above BW)

And finally, same signal amplitude in X and Y direction.
pll gain phase measurement - 0 dB condition

Sure enough, you don’t need to use the X-Y mode, and circular patterns – any two channel representation of the signals will do, as long as their amplitude is measured, and the frequency identified, at which X and Y have equal amplitude (on the X-Y screen, also check the graticule, because the 45 degrees angle is not so easy to judge accurately). That’s the unity gain (0 dB bandwidth) frequency we are looking for. With little effort, the frequency can be measured to about 10 Hz.
The X-Y method has the big advantage that it relies on the full signal, not just certain points, and triggering a PLL signal with a lot of noise can be an issue.

Try to keep the amplitude stable over the range of frequencies measured – by adjusting the signal gen.

Ideally, the 0 dB bandwidth is measure at various frequencies over the full band of your VCO, because the bandwidth can change with tuning sensitivity, etc., of the VCO.

The 0 dB bandwidth is not the only information that can be extracted – also the phase shift is easily accessible. Just measure, at the unity gain frequency, or any other frequency of interest for you, the length of the black and red lines:
pll gain phase measurement - 0 dB condition - phase determination

The phase angle is then calculated by: divide length of red line, by length of black line, in this case, 4.6/6.9 units. Then apply the inverse sin function, to get the phase angle, sin^-1(4.6/6.9)=41.8 degrees. The 0 dB frequency, in this case, was 330 Hz.

A quick comparison with the data acquired using a more sophisticated methods, a HPAK 3562A Dynamic Signal Analyzer.

Gain: 0 dB at 329 Hz – that’s close!
pll test result - gain

Phase: 38.7 degrees – fair enough.
pll test result - phase

A proper PLL setup should provide at least 20 degrees of phase shift (note that this is not the so-called phase margin, which is a property of an open loop). Closer to 0 degrees, and the loop will remain stable, but a lot of noise (phase noise) and osciallation, finally, occasional loss of lock will be the result.

It’s also a good idea to check that the gain function drops off nicely – there are certain cases, where mulitiple 0 dB points exist – you need to look for the 0 dB point at the highest frequency.

Any questions, or if you need something measured, let me know.

PLL measurements continued… ADF41020 locking the Micro-Tel 1295

With the work on the Micro-Tel SG-811 generator PLL mostly completed, some trials with the Micro-Tel 1295 receiver – this instrument has similar YIGs fitted, just needs to be tuned 30 MHz above the actual frequency tuned, because the 1295 is running on a 30 MHz IF (all diagrams have tuned frequencies, not LO frequencies).

After some crude analysis of the schematics, the 1295 seems to be able to handle a bit more PLL bandwidth – so the target set more in the 500 Hz to 1 kHz region, and some calculations were carried out with the ADIsimPLL program, to determine the rough capacitor and resistor values – otherwise, the loop filter is the same as for the SG-811 PLL, also using an OPA284 opamp.

Otherwise, pretty much comparable results (earlier post related to the SG-811), for example (17.8141 GHz tuned/17.8171 GHz LO frequency, Icp setting 6):

Gain (disregard 1 to 10 Hz)
micro-tel 1295 17814100 kHz cpc6 gain

micro-tel 1295 17814100 kHz cpc6 phase

After quite a few of these measurement (doesn’t actually take too long), the results.
adf41020 pll bw phase margin 1295

Phase margin vs. bandwidth
pm vs bw adf41020 micro-tel 1295

Bandwidth vs. charge pump current Icp setting, at various frequencies
bw vs icp at various frq adf41020 micr-tel 1295 pll

Again, a bandwidth frequency^0.7 product could be used to get the numbers down to two parameters – slope and intercept of the bandwidth*frequency^0.7 vs. Icp setting curve.
Finally, suitable Icp settings for a 600 Hz target BW:
bw vs frq adf41020 micro-tel 1295 with Icp adjustment

The result seems quite satisfactory, pretty much constant 600 Hz BW can be achieved over the full 2 to 18 Ghz range, at about 47 degrees phase margin. This should allow for stable operation. No locking issues were observed at any of the frequencies, even with full Icp current.

Fractional-N PLL for the Micro-Tel 1295: ADF4157/ADF5002

After spending most of the day at the beach, some more experimentation – with a fractional-N approach. Two little chips were around from another project, why not give it a try:

(1) The Analog Devices ADF4157, 6 GHz, 25 bit fixed modulus fractional-N PLL – this part is really great, for many purposes. It’s more or less pure magic what these folks at Analog do and achieve.

(2) To make it work up to 18 GHz, a prescaler is needed. Well, unfortunatly, I only have a :8 prescaler (ADF5002) around – this will give 0.25 to 2.25 GHz, for the 2 to 18 GHz input. Not quite ideal, because at 2 GHz it’s getting really into low frequencies for the ADF4157, and the output power of the ADF5002, which is a more-than-sufficient -5 dBm in the 4 to 18 GHz, range, but dropping off to only about -10 dBm at 2 GHz. At the same time, RF input sensitivity of the ADF4157 drops considerably for input frequencies below 0.5 GHz… we will see.

Some calculations:
With a 10 MHz reference clock, and the phase detector frequency set to 1.25 MHz (reference divider=8), this will result in 10 MHz steps, with 2^25 spacings in between. This gives about 0.298 Hz resolution. And moreover, with this setting, 10 MHz steps are possible, with no fractional-N divisor (which can always lead so some rather unpredictable fractional-N spurs).

The circuit – there is no big secret to it, a 5k1 reference resistor to set the charge pump current to 5 mA, and a few 6k8 resistors (0805 SMD) to make the chip compatible to a 5 V digital world. Two SMA connectors – one for the signal, and one for the 10 MHz reference. All wiring is done with 0.08 mm tinned copper wire… hope you have a steady hand. With a drop of epoxy glue, everything is held in place and well-protected.



Tests will follow – currently the loop bandwidth tests are running for the 1295, with the ADF41020 PLL.

Noise and spurs, ADF41020/Micro-Tel SG-811 PLL

After getting things worked out with the loop filter, some quick check for spurious responses. To do such analysis near the noise level, a FFT/dynamic signal analyzer can be used, but I find it somewhat troublesome, and rather use a swept frequency analyzer for any such work that goes beyond 1 kHz. Below 1 kHz, the FFT is hard to beat. One of the few exemptions is the HPAK 3585A spectrum analyzer, which covers from about DC to 40 MHz, and has resolution bandwidth filters of down to 3 Hz (discrete hardware, not software filters), with baseline at -135 dBm, or lower.

The 3585A doing its thing…

The results – 1 to 500 Hz
348_00_0001 to 05
Mainly 60 Hz harmonics – well, will need to keep the cables short (especially the coarse tune cables) and everything far away from mains transformers.

10 Hz to 5 kHz
348_00_001 to 5
Signal at 1 kHz is about -70 dBm, not much. No spurs.

5 to 30 kHz
348_00_5 to 30
Two unexpected spurs – 1st: 19.986 – this is an artifact of the 3585A. 2nd: 18766, this seems unreleated to the PLL (doesn’t change with frequency or divider settings), maybe some switchmode supply stray. Well, down below -100 dBm.

25 kHz (with some 60 Hz harmonic sidebands, -115 dBm) – reference spur, about -93 dBm.
25 khz spur detail

All in all, with some refinement of the software, and a bit of mechanical work to get this all mounted into a nice case, the setup should work find and provide great service.
Sure enough, some direct phase noise measurements on the SG-811 output will eventually follow, once the opportunity is right and the equipment at hand.

Micro-Tel SG-811/ADF41020 PLL: working out the details – loop filter, bandwidth, charge pump currents

Designing a stable PLL is not really a big challenge, with all the simulation tools available, and after you have mastered some basic experiments with the 4046 chip, or similar circuits. For PLL simulation software, I suggest to look at ADIsimPLL, available free of charge, from Analog Devices.
However, stable doesn’t necessarily mean wideband, and exhibiting similar characteristics over a full 2 to 18 GHz band. That’s what we want to achieve here.

First some targets – after reviewing the circuits of the Micro-Tel SG-811/1295, and looking at the stability of the build-in YIGs, I figured that a good PLL bandwidth for this system would be somewhere in the 200-500 Hz region. This would still allow to correct for some mains-induced frequency fluctuations (50/60 Hz), and the frequencies are well below the 25 kHz phase detector frequency used for the ADF41020. Furthermore, the bandwidth should be reasonably stable of the full range of frequencies, with no need to use multiple loop filters, or troublesome switchable capacitors/variable gain amplifiers – all should be operated from a single-ended 15V power supply, to provide 0-10 V for the Micro-Tel 1295, and 0-3 V for the SG-811, from a single little board.

With this in mind, an OPA284 rail-to-rail precision amplifier (low noise, 4 MHz BW, can drive +-6.5 mA) was selected as the active part, and some capacitors (only use good quality capacitors, polymer dielectric, or stable ceramic capacitors, NPO) and resistors put together. There is only one adjustment, the damping resistor in the feedback loop.

Sketch of the schematic
adf41020 sg-811 pll loop filter

How to figure out the loop characteristics? Many pages have been written about this, determining open-loop gains and phase margins, etc., but how to approach this in practice, one you have done the calculations and figured out a setup that basically works? This is where the extra resistor and the two test points (A, B, see schematic) come into play. The resistor close to the output (8k2, this is just a temporary part, only inserted during test – bridged with a piece of view during normal operation) is used to isolate the loop output, from the SG-811 phase lock input (which is nothing else than a heavy VCO=voltage controlled oscillator). A few extra parts are also connected to feed a test signal to the VCO, in addition to the loop filter output voltage.
This test port is intended to disturb the PLL just a bit, without causing loss of phase lock, and measure the response. Such work is best done with a dynamic signal analyzer – I’m using a HPAK 3562a, not because it is the latest model, but because that’s what I have around here in my temporary workshop. It had the old CRT replaced by a nice color LCD screen, and it features a very acceptable noise floor, and gain/phases analysis.

The test setup (please excuse the mess, not too much empty bench space around here)
pll loop test - micro-tel sg-811 - adf41020

Now we just need to work through various frequencies and settings, to better understand the characteristics of the system.
To cover all the YIGs and bands of the SG-811 (which might have unknown variations in tuning sensitivity, noise, etc.), frequencies around 2, 6, 10, 12.5 and 17.5 GHz were chosen for the test (exact values can be found in the worksheet, better not to use even values, e.g., 2.0000 GHz, but to exercise the divider circuits – to see if there are any spurs).

At each frequency, magnitude and phase response was collected, examples:
Gain (disregard the unstable response below 10 Hz, just an artifact)


The interesting point is the 0 dB crossing of the gain trace – the unity gain bandwidth. This is determined for each test condition, and then the corresponding phase is obtained from the phase plot. In this example, BW_0dB is about 380 Hz, with about 20 degrees phase. Why is it so important? Simply because we need to keep this phase gap (of the A and B signals) well above 0 degrees, otherwise, the loop will become unstable-oscillate-massive phase noise of the generator will result.

Some call this the phase margin, so do I, although the whole discussion about gain and phase margins is typically centered around open-loop system, whereas we are dealing with a closed loop here. Fair enough.

Now, after some measurements, and number crunching, the results:

Phase vs. BW, at various frequencies
pm vs bw sg-811 pll
-you can see, the phase margin is virtually independent of frequency, and purely a function of bandwidth. So we can limit all further discussion to bandwidth, and don’t need to worry about phase margin separately. It is also clear from this diagram that we should better stay in the 250-300 Hz bandwidth region, for the given filter, to keep the phase margin above 25 degrees, which is a reasonable value.

Now, how to keep the bandwidth stable with all the frequencies and YIGs/SG-811 bands and sensitivities changing? Fortunately, the ADF41020 has a nice build-in function: the charge pump current can be set in 8 steps (0 to 7), from 0.625 to 5 mA (for a 5k1 reference resistor) – and setting the charge pump current (Icp) is not much else than changing the gain of the loop filter. The gain, in turn, will change the 0 dB bandwidth in a fairly linear fashion. Note: typically, the adjustable charge pump current is used to improve locking speed – at wider bandwidth, and mainly, for fixed-frequency applications – but is is also a very useful feature to keep bandwidth stable, for PLL circuits that need to cover a wide range of frequencies, like in the case of the SG-811.

The next result – bandwidth vs. Icp setpoint
sg-811 pll bw vs charge pump current at various frequencies
-looking at this diagram, the bandwidth is not only a function of Icp, but also a function of frequency. For the larger frequencies, the bandwidth is much lower. Some calculations, and it turns out that the product of bandwidth, multiplied with frequency to the power of 0.7 (a bit more than the squareroot) is a good parameter that gives an almost linear vs. Icp (see worksheet, if interested).
adf41020 pll bw phase margin

After all the measurements, things are now pretty clear – if we set the Icp current right, BW can be kept stable, over almost the full range, without any extra parts and switches, and about 300 Hz seems to be a reasonable compromise of PLL speed and stability.

Estimated PLL bandwidth (0 dB), using the Icp current adjustment of the ADF41020
bw vs frq with charge pump current adjustment
At the lowest frequencies (2 GHz range), the BW is found a bit larger than desired, but still, the loop still has 20 degrees margin.

Well, with all the phase margins and uncertainties, is the loop really stable enough? To check this out, what is typically done is to first try a few odd frequencies, at the start, end and in the middle of each band and monitor the VCO control voltage with a scope, for any oscillations or otherwise strange behavior. Then try a few small frequency steps, and see how the loop settles. This all went without any issues.

Still, to be sure, especially close to 2 GHz (increased bandwidth), a test was performed by injecting a 100 mV (nominal) squarewave, 10 Hz, via the test port mentioned above. The loop output spectra showed that this worked, and that the 10 Hz contribution is significant, while still not swamping everything else and driving the loop out of lock right away.

Power spectra with test signal on (upper diagram), and off (lower diagram).
pll power spectra

There are some 60 Hz/harmonic 60 Hz spurs, mainly due to coupling of 60 Hz to the coarse tune line, which is just a plain coax cable that doesn’t provide any good shielding vs. 60 Hz (or 50 Hz, in Europe) interference.

Needless to say, the PLL will not stop working right away when the phase hits 0 deg at the 0 dB point (see above, phase margin vs. bandwidth plot – even at negative phase, measurement was still possible – as long as the amplitude of the test signal is kept small).
There will be signs of instability, and this is what this test reveals. So the frequency was set again to 2.2221 GHz, and the charge pump current Icp increase step by step, from 0 to 5. At 6 and 7, no phase lock could be achieve – fully unstable loop.

Step response (AC component only, square wave, 10 Hz at nominal 100 mV, supplied to test port)
pll step response 2.2221 ghz 100 mV
Icp=0 – this is the most stable condition, phase margin is about 20 degrees. Already at Icp=1, phase margin of about 3 degrees, stability is much compromised/considerably more noise, not only for the step response, but also during the steady portions. At Icp=2 and above, phase margin is negative, still, phase lock is robust (will not re-lock, once lock is lost), and the pulse response suggests to stay away from such regions.