Tag Archives: sine fitting

Ultralinear ADC – some mathematical review

Working a bit deeper in the topic of ADC calibration, and doing some math some preliminary conclusions reached so far:

(1) Analyzing the ADC noise, requirements to suppress mains noise, and the effective number of bits available from the ADS1211, I figure that running the ADC at 60 Hz data rate would be the best choice (50 Hz in Europe, will be factory-settable in the final apparatus), and a data volume that can be managed easily. To get the best ENOB per reading, the ADS1211 is run in 16x turbo mode, 2083 decimation, 4 MHz clock (will be 16 MHz:2 later, running on one clock with the controller, just lacking a 8 or 10 MHz crystal atm).
59.98 Hz resulting frequency, close enough. For 50 Hz, we will run at 2499 decimation, and get exactly 50 Hz data rate.
With a 4 MHz clock, about 22 bits effective resolution, with 10 MHz, even 23. Not bad, but I’m sure the test setup will be a bit worse (better reference, shielding, improved power supply needed, for the analog supply -low noise, will be based on LM723 – which is actually still a very well performing circuit, and much lower noise than the common 78xx regulators).

(2) Calibrating an ADC, to, say, 21 bit effective resolution, which two million noise-free counts, 128 dB SNR, with a sine wave by generating a histogram: it will take a long time. A very long time. 60 Hz means 5 million samples a day, would need to collect readings for several day – doesn’t seem practical.

Next steps:

(1) Noise characterization, shorted, and with a somewhat noise signal – this will tell us a bit about the nature of the local non-linarities, by comparing the noise histogram, with Gaussian noise. Will also show missing codes, if any.

(2) Do an in-depth characterization of linearity for one exemplary ADS1211, might need above-mentioned improments to reduce noise effects in the test setup, and also needs low jitter clock source (current crystal should be low jitter, but might want to change to 8 MHz before going to a lot of trouble with characterization. Key question is, for the ppm-level linearity – is this locally worse at certain codes-in certain small code regions, or evenly spread over all codes, just needing a few “pin points” for a correction algorithm, to get the linearity down to 1-2 ppm level.
After review of the literature, a method of fitting sine-wave data (similar to histogram method, but rather than just counting the bins, fitting the data – voltage vs time – to an ideal sine wave, with a 4 parameter fit, and using the residuals for non-linearity estimation; fit might be done piece-wise, for big datasets, to allow for some small frequency drift of the sine source; might also cut-off the uppermost and lowermost bins, minimum and maximum voltages).

(3) Decide, based on the data of item (2) how many measurements/level will need to be measured to continuously monitor the performance and adjust correction constant. In the final system, a 16-bit ultrahigh precision DAC/programmable voltage source. Such kind of circuit can be build from discrete low-drift low-tempco resistors like Alpha Electronics MA series, and a precision low noise/low drift reference like the LTZ1000 or LM399, and a few opams, like LTC1051.
It would be fairly easy to sample these 16 voltags with the proposed 4-ADC scheme, and calculate corrections coefficients, at the 16 points, to compensate the the major part of the non-linearity.