Tag Archives: USB RTL SDR

USB RTL SDR 28.8 MHz Reference: dividers, PLL, success

With the 28.8 MHz VCO design established, all we need to move this project on are divers for the 28.8 MHz (VCO) and 10 MHz (Reference) signals, a slow-acting PLL, and some auxilliary circuitry to feed the 28.8 MHz back to the RTL SDR.

The 28.8 MHz and 10 MHz signals are AC coupled with about 1 kHz input impedance, this is quite common for any 10 MHz reference signal input (used for various kinds of test equipment). These signals are then amplified/limited by unbuffered inverters, 74HCU04. This is a very cost-effective and easy solution, the HCU04 has push-pull outputs, and input clamping diodes. Still, some clamp diodes have been added for the 10 MHz input, just in case.

28.8 mhz divider chain schematic

Looking at 28800 kHz, and 10000 kHz, 400 kHz is the largest common denominator. Accordingly, we need :72, and :25 division factors.

Division of the 10 MHz down to 400 kHz is accomplished by two 74LS90, but you can use other TTL decade dividers, these were just the circuits I had in stock.
28.8 to 400, a bit more tricky, first, divided by 8, using a 74LS293, and another LS293 that has two diodes, acting as an “OR”, to reset the counter when count 9 is reached.

Both 400 kHz signals are then compared use a flip-flop phase comparator, conveniently packaged in a 4046 PLL. For convenience, and to avoid digital noise on the 12 V rail powering the VCO, the 4046 is powered only from 5 V. This somehow limits the tuning output range, from close to 0 V, to about 3.1 V.

The loop filter is very slow acting, tens of seconds, because the objective of this PLL is to correct long-term drift of the 28.8 MHz reference, introduced by temperature, Xtal drift, etc., but otherwise not to impact its noise and oscillation characteristics.

28.8 mhz pll and loop filter schematic

The VCO (see earlier post, VCO design) uses a fixed capacitor to set the tuning offset, this was changed to 4.4 pF, and finally to 2.2 pF, to properly center the tuning voltage (V_tune, output of the PLL loop filter buffer) within the 4046 output range, at roughly 1.7 V.
Extentensive testing was carried out the ensure that the VCO starts up properly, even if extreme V_tune voltages are applied; as the 28.8 MHz Xtals used in the USB RTL SDR devices may vary, you will need to check the required tuning range and pullability of the Xtal. Some Xtals oscillators will stop oscillating, if you pull to frequency up or down too much, which might happen during PLL start-up. This can lead to an undesirable lock-up condition.

Here are the tuning characteristics, for 2p2, and 4p4 pF VCO capacitor values.

28.8 mhz tuning

This is the divider and PLL board. Sure it would be much nicer to have everything completely separated, in shielded cans, etc., but I did not go to such effort. Later testing will reveal if it has any bad consequences for the 28.8 MHz phase noise, but so far, I don’t see much noise – will do a more in-depth comparison later.

28.8 mhz pll boad

USB RTL SDR 28.8 MHz Reference: VCO design established

A quick update on an earlier post, USB RTL SDR 28.8 MHz Reference: VCXO, development of a low-noise 28.8 MHz is now complete. A BB159 varicap has been selected for the voltage tuning control, and it works nicely, even within a 10 V tuning range. This is a UHF varicap diode, C_28V of about 2.1 pF, 9:1 ratio.

bb159 varicap

The updated schematic – the test setup still shown here still uses a few through-hole parts, put most of the RF caps are SMD 0805. J310 J-FETs are used, both for the oscillator, and the amplifier – mainly because of their low cost, and they are widely available.

28800 vco schematic

This is the test setup – test signal provided by a 8904A, and frequency measured by a 5372A Time and Frequency Analyzer, 4 s gate time.
28800 vco test

That’s the tuning curve, it happened to be at 28.800000 MHz, for about 5.5 Volt, nicely centered within the tuning range. No need to worry about the deviation from linear slope, the PLL will have a very long time constant, and the non-linearity of the tuning curve won’t have any impact on the VCO performance.
28800 vco tuning curve

A nice additional feature – this VCO circuit works with the default 28.8 MHz crystal (which is actually no so bad, it is quite stable over temperature, at least the samples I have tested here, taken from cheap USB RTL SDR sticks). +-700 Hz range, +-25 ppm, should be pretty much sufficient to keep the VCO locked over a wide range of temperatures. If not (for other 28.8 MHz that might be around out there), two of the varicaps can be used in parallel, and the C* capacitor adjusted a bit; pullability of the xtal is pretty good, +-1.8 kHz is easily possible. It is best not to use a trimmer cap, but to solder-in suitable capacitors, to keep noise down, and stability up.