Tag Archives: YTO driver

YTO YTF Driver: 0..250 mA, 16 bits resolution

Quick update on the YTO/YTF driver board – with 16 bits of resolution. Assembly, is complete, and basic function has been checked – digital control test will follow tomorrow.
Current is settable from 0 to 250 mA, with 65535 counts of resolution – about 3.8 Microamps per LSB. All has been build to minimize noise, with heavy filtering on the supplies. The DAC is run from a dedicated 5 V supply, with a 2.5 V precision reference, 1 ppm/K, MAX6325ESA+.
The U to I converter is powered by 11.4 V – provided by a LM317 voltage regulator.
Switching element is an IRF730, operated as a series variable resistance in series with the coil.

YTO YTF driver 2x250 mA 16 bit

YTO YTF driver 2x250 mA 16 bit schematic

Looking at the BoM, the parts sum up to about USD 35 plus board, not bad – target is to stay below about $100 for the final assembled unit, which will be achievable, no issue. Main cost comes from the MAX reference, and the DACs (DAC8830), almost USD 22.

To come: bandwidth testing

YIG tuned oscillator (YTO) / YIG tuned filter (YTF) driver: digitally controlled current source

For a digitally controlled YIG oscillator and filter, a driver is needed that can convert serial data from a microcontroller to a well defined, stable, and low noise current.
Bandwidth of the circuit should be a few 100 Hz, and maximum current in the 300 mA range, so it needs to run of a reasonably high supply voltage, otherwise, the inductance of the coil will limit the slew rate. The YTO needs about 120 mA full scale, the YTF about 260 mA.

I might do some fine tuning on the DACs later or change the current sense resistors for a 2.5 V drop at close to max current, for best signal to noise ratio, but for the test circuit, 10 Ohm RH-25 resistors will be used. The current sense resistors are a very critical part – they need to be low drift, over time, and over temperature, regular resistors, with 100 ppm/K or more will only cause drifting frequencies, and trouble.

Here, the draft schematic, as-build:
YIG driver schematic dac control - u to i converter

That’s the test setup, with +20 V and -10 V power supply, for the YIG. In the final setup, there will be independent, filtered and regulated supplies for low phase noise.

YTO driver test setup

The circuit is driven by a HP 8904A signal generator, with independent adjustment of offset and voltage. Here, the output at 70 mA current, with a +-1 mA amplitude variation:

YTO output 70 mA +-1 mA
YTO is a HP 5086-7259, 2.0-4.5 GHz (nominal).

So, about +-40 MHz – close to expected +-35 MHz.

Bandwidth analysis will follow.

Here a quick calculation of the DAC resolution, 1 LSB will be about 0.13 MHz, more than sufficient for the DAC tune. The DAC used, a DAC8830ICD has typical +-0.5 LSB non-linearity, max +-1 LSB. Additional tuning will be easily accomplished by the FM coil, using a PLL.

yto ytf dac calculator