Tag Archives: 28.8 MHz

R820T/RTL2832U USB SDR: Various hacks and measurements

USB RTL SDR 28.8 MHz Reference: dividers, PLL, success

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With the 28.8 MHz VCO design established, all we need to move this project on are divers for the 28.8 MHz (VCO) and 10 MHz (Reference) signals, a slow-acting PLL, and some auxilliary circuitry to feed the 28.8 MHz back to the RTL SDR.

The 28.8 MHz and 10 MHz signals are AC coupled with about 1 kHz input impedance, this is quite common for any 10 MHz reference signal input (used for various kinds of test equipment). These signals are then amplified/limited by unbuffered inverters, 74HCU04. This is a very cost-effective and easy solution, the HCU04 has push-pull outputs, and input clamping diodes. Still, some clamp diodes have been added for the 10 MHz input, just in case.

28.8 mhz divider chain schematic

Looking at 28800 kHz, and 10000 kHz, 400 kHz is the largest common denominator. Accordingly, we need :72, and :25 division factors.

Division of the 10 MHz down to 400 kHz is accomplished by two 74LS90, but you can use other TTL decade dividers, these were just the circuits I had in stock.
28.8 to 400, a bit more tricky, first, divided by 8, using a 74LS293, and another LS293 that has two diodes, acting as an “OR”, to reset the counter when count 9 is reached.

Both 400 kHz signals are then compared use a flip-flop phase comparator, conveniently packaged in a 4046 PLL. For convenience, and to avoid digital noise on the 12 V rail powering the VCO, the 4046 is powered only from 5 V. This somehow limits the tuning output range, from close to 0 V, to about 3.1 V.

The loop filter is very slow acting, tens of seconds, because the objective of this PLL is to correct long-term drift of the 28.8 MHz reference, introduced by temperature, Xtal drift, etc., but otherwise not to impact its noise and oscillation characteristics.

28.8 mhz pll and loop filter schematic

The VCO (see earlier post, VCO design) uses a fixed capacitor to set the tuning offset, this was changed to 4.4 pF, and finally to 2.2 pF, to properly center the tuning voltage (V_tune, output of the PLL loop filter buffer) within the 4046 output range, at roughly 1.7 V.
Extentensive testing was carried out the ensure that the VCO starts up properly, even if extreme V_tune voltages are applied; as the 28.8 MHz Xtals used in the USB RTL SDR devices may vary, you will need to check the required tuning range and pullability of the Xtal. Some Xtals oscillators will stop oscillating, if you pull to frequency up or down too much, which might happen during PLL start-up. This can lead to an undesirable lock-up condition.

Here are the tuning characteristics, for 2p2, and 4p4 pF VCO capacitor values.

28.8 mhz tuning

This is the divider and PLL board. Sure it would be much nicer to have everything completely separated, in shielded cans, etc., but I did not go to such effort. Later testing will reveal if it has any bad consequences for the 28.8 MHz phase noise, but so far, I don’t see much noise – will do a more in-depth comparison later.

28.8 mhz pll boad

R820T/RTL2832U USB SDR: Various hacks and measurements

USB RTL SDR 28.8 MHz Reference: VCXO

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One of the shortcomings of the USB RTL SDR devices is the build-in oscillator. It is actually very stable and sufficient for all kinds of everyday uses, but I am using these SDR devices for narrowband applications, with down-converted microwave signals. So utmost frequency stability is a must.

Not only needs to frequency be stable, it is also a good idea lock all oscillators to a common reference, which typically is derived from a 10 MHz rubidium source (like in my lab), or a GPS-controlled VCXO.

How to get from 10 MHz to 28.8 MHz – well, not all that difficult, but needs quite a few parts. First, we need a circuit that can receive 10 Mhz signals, and clean them up and prepare them to be used by a PLL. Then, we need a VCXO (voltage controlled quarz oscillator) that can be tuned by the loop filter of the PLL to keep it at 28.8 MHz. The loop BW will be very very narrow, a few Hz at maximum. Comparator frequency can be up to 400 kHz, the largest common divider of 10000 and 28800; but I might select a value more like 100 kHz which can be readily derived from a 10 Mhz reference. There are plenty of programmable PLLs around, but I might just use a hardware solution here (only need to put together :288 and :100 dividers using some TTL logic).

The circuit-
rtl sdr 28-800 MHz ref pll

– nothing too fancy, and still needs some fine tuning. The xtal, it’s the original part de-soldered from the RTL SDR stick. These are actually pretty stable and well-behaved, at least for the devices I sourced from China.

The circuit employs a Pierce oscillator, build around a J310 FET. This is coupled into a common-bias amplifier, another J310, which provides the low output impedance. A matching network is added the make the circuit rather insensitive to changes in the load impedance. The circuits draws about 20 mA at 12 V. Not quite a power safer, hey, but this is not the objective here.

The items circled are just temporary parts, will need further optimization.

The big question – tuning range (pullability) of the xtal. Ideally, it should be a few 10s of ppm, to give the PLL some room to operate, and to account for aging effects over the years. Temperature-induced changes are on the order of a few ppm (see earlier post); but there is also drift, and other factors.

A quick test with some capacitors, and, stable oscillation can be found in a range of -1.8 to about 1.8 kHz around the 28.8 center frequency, this is quite satisfactory.

rtl sdr ref vcxo circuit

At the moment, still run with fixed capacitors, but I will add a varactor network to provide about 8 to 40 pF tuning capacity, by voltage input.
In an effort to keep phase noise down, I might employ a circuit used a lot for earlier projects, with anti-parallel varactor diodes.

rtl sdr ref 10 pf

rtl sdr ref 37 pF

The spectra look pretty clean, and the power is as expected, about -10..-6 dBm. I will use this output to drive the PLL, and add another amplifier to drive the RTL SDR R820T reference input – well shielded from everything else to avoid spurs from the divider and PLL circuits.

A quick test of the phase noise – hooked it up to a 3585A Spectrum Analyzer – there are some mains spurs, which will be reduced by adequate filtering once the circuit is fitted to a shielded box. Other than that, nothing really suspicious. All very close or at the noise floor of the 3585A.

10 pF sdr ref0

3585a noise floor