Tag Archives: ADF4157

Micro-Tel MSR-904A Microwave Receiver: reducing phase noise – phase detector frequency

Like with most PLL build, there a quite a few things that can go wrong – the result: a lot of phase noise. For the current setup, all precautions had been taken to avoid bad surprises – low noise supplies, well-proven loop filter amplifier, low noise DAC, adequate cables. And, phase lock was quickly achieved (see last post).
For more detailed analysis, both the 160 MHz and the 21.4 MHz IF signals of the MSR-904A are fed to analyzers. For the 160 MHz, to a RTL SDR stick, just for the rough picture, and the 21.4 MHz, to a 3585A analyzer. The 3585A has very low noise, ideally suited to look at phase noise, except if you are working the ultra low noise segment.

Initial finding – phase noise is down at about 60 dBc at >10 kHz offset, dropping off as expected, but the close-in noise is really bad. Close in noise often related to the phase detector, or the reference. Substituting the 10 MHz reference from the EIP545A by a really low noise HP 10 MHz OCXO didn’t change much. So to high noise level must be connected to phase detector.

With the detector set to 1.25 MHz (:8 reference divider), there we can gain quite a few dB of noise supression, by increasing the detector frequency (within limits, doubling the detector frequency lowers the associated noise contribution by about 3 dB). And, even more, we can check out the reference doubler, which is a build-in feature of the ADF4157. With the doubler in use, it needs to be ensured that the duty cycle of the reference is close to 50%, but this is ensured by the OCXO anyway.

The ADF4157 can handle phase detector frequencies of up to 32 MHz, no issue at all with 20 MHz. The only downside – more fractional-N spurs – channel spacing for integer only dividers is now 160 MHz, rather than 10 MHz….

msr pll phase noise

msr pll phase noise averaged

Red and green traces – you can see, the PLL is completely detector noise saturated within the bandwidth.

Other traces – all with a phase detector frequency of 20 MHz – and at different charge pump currents (CPC). A CPC of 15 corresponds to a 5 mA current. This has direct impact on the phase loop cut-off frequency. There is some peaking, at 2 kHz (dark blue trace, CPC 1), and at about 7 kHz, light blue trace, CPC 10.

Comparing the yellow and magenta traces – these differ by the 10 MHz reference signal source only (yellow uses an HP 10811 OXCO, magenta uses the EIP 545A build-in reference which is pretty stable, but rather noisy). In the curent setup, both references yield very similar results – accordingly, the noise within the PLL bandwidth is dominated by the PLL cirucit itself, and the phase detector, not the reference source.

There are some mains-related spurs at 60 and 180 Hz, but these might just be due to the temporary cabling and lack of a proper case. The circuit is fully exposed, tranformers closeby, etc. For the final setup, all cables will need to be as short as possible, especially for the pretune voltage (which is about 2 MHz per Volt – 2 kHz noise for 1 mV!).

Credits go to KE5FX for the great PN.EXE phase noise measurement tool, invaluable for any such work!

Micro-Tel MSR-904A Microwave Receiver: phase lock test, YIG driver bandwidth modification

Some final parts added to the MSR-904A digital interface/PLL: the actual PLL circuit (frontend), an Analog Devices ADF4157 fractional-N PLL, together with an ADF5002 8:1 prescaler. The phase detector is set at 1.25 MHz, to allow 10 MHz integer-only steps. Some experimentation with other phase detector frequencies might follow later.

Here – the schematic of the PLL frontend. The circit is wired point-to-point, sure enough, with VERY short wires, soldered using a microscoped – hope you have a steady hand. After a quick test (using the MUX output of the ADF4157), the wires and the very tiny ADF gadgets, all sealed with a few drops of epoxy.

msr pll adf5002 adf4157 schematic

On the main board, the PLL loop filter. Build around the remaining half of the already installed OPA2703 (other half used for the DAC output buffer).

msr pll loop filter

With all these parts now put together, to do some basic tests on the PLL – a Gigatronics 605 Microwave Synthesizer was connected to the MSR-904A input, and the LO sample output of the MSR-904A connected to PLL. A sample of the “LO sample” taken by a broadband -10 dB coupler is used to monitor the frequency, using an EIP 545A. The 10 MHz reference output of the EIP is used as the ADF4157 reference.

msr pll phase lock test setup
msr pll test setup 2

The MSR-904A down-converts the signal to a first 250 MHz IF (by fundamental LO), the 250 MHz IF is then mixed with 410 MHz (this can be locked to a 5 MHz signal – not locked at the moment, but the signal is very clean and stable anyway).

The 160 MHz 2nd IF is available at the rear panel, and connected to a R820T RTL SDR. This is a very handy method to monitor noise, and do some basic adjustments on the PLL. Using headphones – and the human ear as a phase noise meter… more quantitative analysis to follow.

Here, the transition from manually controlled CW mode, to PLL controlled mode.
msr-904a locked at 7250 mhz lo

A close-up:
msr-904a locked at 7250 mhz lo 2

For these tests, the LO was locked at 7.25 GHz, receiving a signal at 7.0 GHz (SDR offset set to about 160 MHz).

Note – same as for the Micro-Tel 1295, and the SG-811 – the YIG driver has a bandwidth limit (by a 100 uF Tantalum capacitor – and a 499 k resistor!) that is controlled by a reed relais on the YIG driver. This doesn’t allow low phase noise operation, even with the best PLL. Well, 100 uF is a bit too much. Therefore, a 100 n capacitor was added – this is enough to suppress most of the noise of the YIG driver stage, and still the circuit remains fast enough for full band sweeps at moderate scan rates. Might modify this later, by adding a bit of logic that adds the 100 n capacitor only when the external frequency control is active, but disconnects it during full band sweep, etc.
msr-904a YIG driver board

Micro-Tel MSR-904A Interface/PLL: low noise power supplies for PLL and pretune circuits

Recently, some pretune DAC and microcontroller circuitry has been build, see earlier post. This is now basically functional, however, we need to confirm that is is really working as desired. Never trust any circuits just build – especially when it comes to “unpredictable” aspects like noise. The parts used, they will most likely perform up to their specification, but there can be all kinds of hidden issues that will later on lead to lengthy troubleshooting of phase noise or spur issues.
From experience, power supply related noise is one of the most severe and troublesome item, if not taken care of at an early stage of design, or prototype construction.

Many articles exist on how to characterize power supply noise, especially at very low levels. This is not really what we need here, because we are talking about a real-world circuit that will later work with a mains power supply, in a reasonably well shielded case. So, our standard will be the lowest noise analyzer I have around here, an HPAK (HP Agilent, now: Keysight) 3585A Spectrum analyzer. This has pretty low noise anyway, down to -137 dBm for a 3 Hz bandwidth.

msr pll 3585a noise floor

The only downside of the 3585A, it is about 80 pounds – you will need a sturdy bench and a strong assistant to lift it.
msr pll 3585a analyzer
As a side note: The instrument on my bench, it has an interesting sticker, formerly owned by ST (STMicroelectronics, formerly known as SGS-Thomson as printed on the cal label). ST does a pretty massive amount of R&D in the field of semiconductors, and has a long-standing history of inventions. Well, fair enough, I got this instrument in bad shape, seems to have passed through many hands since ST time, but it is now fully repaired and calibrated, providing great service.

Step (1) – analysis of the circuits already build. Just some 0-25 kHz spectra.

Noise floor, probe grounded at AGND.
msr pll agnd floor 25k

317 regulator output (11.4 V)
msr pll 317 noise 25k

– well, much worse than expected! More than 30 dB above the noise level!!

Well, after scratching my head for a while – and doing some measurements around the not-too-complicated 317 circuit, one 22 uF cap was added, to the adjustment input. Ideally, for best frequency response, use a low ESR cap, with wide response, like a tantalum or multilayer ceramic. I could not be bothered, just used a plain electrolytic.

Improved schematic:
msr pll power supply updated
(red frame shows additional cap)

The result:
msr pll 317 noise 22 uf ref bypass 25k
A 20 dB improvement, fair enough!

Step (2) – PLL low noise power supplies (2x 3.1 V)

The PLL (an ADF4157 fractional-N synthesizer with ADF5002 prescaler) requires a +3.1 V power supply (2.7 to 3.3 V for the ADF4157, 3.0 to 3.6 for the ADF5002 – so I decided on 3.1 V for both devices). Also, we need a charge pump supply, for the ADF4157. This can be up to 5.5 V, but for simplicity of design, and to follow earlier (rather commercial) designs I did fully using 3.3 V technology, another independent supply is required, for 3.1 V.

These supplies need to very low noise, supply line noise will end up at the charge pump output, increasing phase noise. Glitches on the PLL supply lines can cause all kinds of issues, even the reliability of the circuit might be compromised (miscounting of the prescaler, etc.).

Quite a few more recent parts exist to provide about 3 V regulated output (see TI, Analog, LT), but these devices are non too widespread, and not much better, if not even worse than a trusty old part: the LM723 (aka µA723) regulator. This has a low noise reference build in, and should provide much better performance than any 3-pin regulator.

The schematic – main DC input, and 3.1 V low noise power supply section:
msr pll low noise power supply 3 volt

That’t the little board, during test:
msr pll test setup

And here, we have the results – all tests now using 1.2 KHz stop frequency (not much going on at higher frequencies), 10 Hz resolution bandwidth, 3 Hz video bandwidth, and, using the noise measurement function of the 3585A – this directly measures and calculates the noise level, at a given frequency, for a 1 Hz bandwidth. Very handy for conversion to nV/sqrt-Hz (nV divided by square-root Hertz is a common way of expressing power supply noise).

Noise floor:
msr pll noise floor 1k2 grounded at agnd

The 317 output (11.4 V) – supply of the pretune DAC circuit and amplifiers, and for the PLL active loop filter
msr pll 317 noise 1k2

The 7805 output (5 V) – digital supply, DAC supply
msr pll 7805 noise 1k2

The 723 output (3.1 V) – Vdd section
msr pll 732 vdd 1k2

The 723 output (3.1 V) – Vp section (charge pump supply)
msr pll 732 vp 1k2

A converter worksheet, to relate the dBm numbers, to nV/sqrt-Hz (calculation also has provisions to convert from other bandwidth – not considering a few extra dB to account for the averaging nature of the detector, etc. – we rely on the 1 Hz normalized value of the 3585A anyway, just in case you need to convert from other BW, please keep dectector response related offset correction, if the task requires such levels of accuracy).
power supply noise calc 3585a

Converted values
-141 dBm – about 20 nV/sqrt-Hz (Vp supply) – very close to noise floor of the setup, the LM723 still seems good enough!
-122 dBm – about 180 nV/sqrt-Hz (5 V, 11.4 V supply)

Also, quick look at the DAC pretune output – at the OPA2703 scaling amplifier output:

msr pll dac amp vtune output 1k2
Virtually, below noise floor.

Note: there are some litte contributions at 60 Hz/180 Hz from mains. These are due to the test setup/signals picked-up by the test cables – don’t seem to originate from the circuit itself.

PLL characterization – final results for the Micro-Tel SG-811 and Micro-Tel 1295 circuits

After some experimentation, measurements, etc. – as described before, time to wrap it up.

The PLL loop filter output is now connected to the phase lock input (the additional 1 k/100 n low pass in the earlier schematic has been omitted), with a 330 Ohm resistor in series. This will remain in the circuit, because it’s handy to characterize the loop, and to provide a bit of protection for the opamp output, in case something goes wrong, to give it a chance to survive.

With the charge pump current adjustments now implemented in the software, that’s the result, all pretty stable and constant over the full range.

The SG-811 signal source
micro-tel sg-811 pll bandwith vs frequency

The 1295 receiver
micro-tel 1295 pll bandwidth vs frequency

Micro-Tel SG-811 PLL: frequency response
sg-811 final gain

sg-811 final phase

Micro-Tel 1295: frequency response
1295 pll final gain

1295 pll final phase

Fractional-N PLL for the Micro-Tel 1295 receiver: some progress, more bandwidth, two extra capacitors, and a cut trace for the SG-811

Step 1 – Programming of the ADF4157, no big issue – fortunately, all well documented in the datasheet. The 1.25 MHz phase detector frequency selected will allow tuning in integer-only (no fractional divider) 10 MHz steps (considering the :8 ADF5002 prescaler).

One sigificant difference to the ADF41020 – the ADF4157 uses 16 steps for the charge current control (0=0.31 mA to 15=5.0 mA).

Step 2 – Checking for lock at various frequencies – in particular, at the low frequencies – the thing is running really at the low edge, 250 MHz input for the ADF4157. However, despite all concerns, no issues, prescaler and PLL are working well even at the low frequency. Quite a bit of noise! Not out of focus…
1295 noisy signal

The PLL is locking fine, but still, significant noise in the loop, and also visible in the 1295 scope display, with a very clean signal supplied to the receiver… bit of a mystery. When the PLL is disengaged, and the 1295 manually tuned – no noise, just some slow drift.

Step 3 – Increased loop bandwidth to about 8 kHz, even more noise – seems to PLL is working against a noisy FM-modulated source…. a mystery. Checked all cables, nothing is changing when I move them around.

Step 4 – Some probing inside of the 1295, and review of the signal path for the PLL tune and coarse tune voltages. And, big surprise – there is a relais (K1) on the YIG diver board, and this disengages a low-pass in the coarse tune voltage line – it is a 499k/22 µF RC, several seconds time constant.

See the red-framed area:
micro-tel 1295 A3B9 YIG driver loop damping

Tackling this through a lowpass in the coarse tune feed line (from the coarse tune DAC) didn’t change a thing – the noise is getting into the YIG driver from instrument-internal sources, or partly from the opamp (U5, LM308) itself, when it is left running at full bandwidth. As a side comment, note the power amplifier – it is a LH0021CK 1 Amp opamp, in a very uncommon 8 lead TO-3 package. Hope this will never fail.

Usually, I don’t want to modify test equipment of this nature, because there is nothing worse than badly tampered high grade test equipment. All conviction aside, 2 X7R capacitors, 100 n each, were soldered in parallel to the R38 resistor, so there will be some bandwidth limitation of the YIG driver, even with the K1 relais open.
micro-tel A3B9 YIG driver board - modified

With these in place – the noise issue is gone.
1295 clean signal

Now, triggered by this discovery – the SG-811 uses a very similar YIG driver board, which also has a low pass engaged, in the CW mode – however, not in the remotely controlled CW mode, with externally settable frequency… easy enough, just one of the logic traces cut, and now the filter stays in – don’t plan on sweeping it with a fast acting PLL anyway.

Back to the fractional-N loop: after some tweaking, the current loop response seems quite satisfactory. Set at 3 kHz for now, with plenty of adjustment margin, by using the 16-step charge pump current setting of the ADF4157. Getting 45 degrees phase margin (closed loop) at 3 kHz – therefore, should also work at higher bandwidth. Will see if this is necessary.

PLL gain
1295 fractional-n loop mag

PLL phase
1295 fractional-n loop phase

Fractional-N PLL for the Micro-Tel 1295: ADF4157/ADF5002

After spending most of the day at the beach, some more experimentation – with a fractional-N approach. Two little chips were around from another project, why not give it a try:

(1) The Analog Devices ADF4157, 6 GHz, 25 bit fixed modulus fractional-N PLL – this part is really great, for many purposes. It’s more or less pure magic what these folks at Analog do and achieve.

(2) To make it work up to 18 GHz, a prescaler is needed. Well, unfortunatly, I only have a :8 prescaler (ADF5002) around – this will give 0.25 to 2.25 GHz, for the 2 to 18 GHz input. Not quite ideal, because at 2 GHz it’s getting really into low frequencies for the ADF4157, and the output power of the ADF5002, which is a more-than-sufficient -5 dBm in the 4 to 18 GHz, range, but dropping off to only about -10 dBm at 2 GHz. At the same time, RF input sensitivity of the ADF4157 drops considerably for input frequencies below 0.5 GHz… we will see.

Some calculations:
With a 10 MHz reference clock, and the phase detector frequency set to 1.25 MHz (reference divider=8), this will result in 10 MHz steps, with 2^25 spacings in between. This gives about 0.298 Hz resolution. And moreover, with this setting, 10 MHz steps are possible, with no fractional-N divisor (which can always lead so some rather unpredictable fractional-N spurs).

The circuit – there is no big secret to it, a 5k1 reference resistor to set the charge pump current to 5 mA, and a few 6k8 resistors (0805 SMD) to make the chip compatible to a 5 V digital world. Two SMA connectors – one for the signal, and one for the 10 MHz reference. All wiring is done with 0.08 mm tinned copper wire… hope you have a steady hand. With a drop of epoxy glue, everything is held in place and well-protected.



Tests will follow – currently the loop bandwidth tests are running for the 1295, with the ADF41020 PLL.