The Si5351 series of silicon-VCOs and clock generators is a quite remarkable achievement of technology. Earlier on, we needed two sets of dividers, PLL control logic, and a VCO – essentially a box full of parts – to realize the same purpose: generating one clock, from another.
While being quite adaptable to all kinds of circumstances and uses, the Si5351A (which is the cheapest, and most common chip – all the others have so many pins, and are in such small package that they are hard to use) has some limitations.
(1) It only has a crystal (XTAL) input, specified over a narrow frequency range. 25 to 27 MHz. Some forum comments suggest that there is a tuned oscillator inside, only working at such frequency, Myth or Truth? For my particular application, I need to drive it by a 10 MHz external clock, because that’s the main frequency source and signal I have available.
(2) The VCO range, 600 to 900 MHz should be selected, according to the instructions. Any chance to use lower frequencies, in case this is needed to get integer-only division ratios? Or higher frequencies? What are the limits?
To test the Si5351A, we can use one of the cheap break-out boards. I used the CJMCU-5351. Including SMA connectors, just a few bucks! I can’t really make it any cheaper, and this board also has level translators, and a 3.3 V supply, which is needed because the digital control will be running on good old 5 Volt logic. The I2C control signals are conveniently provided by a Atmel Atmega168PA controller, from a shared 5 Volt I2C bus.
Some modification is necessary – we need to remove the crystal, and add a small SMD capacitor, and a short wire. Once of the outputs, we cut the trace an re-purpose it as an input.
The schematic, it is quite similar to the connection method suggested in the Si5351 datasheet.
Actual modification and test circuit:
Obviously, to test the Si5351 over a range of reference input, we need to set the internal dividers (to lock the VCO to the reference clock input, and to divide it down to a suitable output frequency) to suitable values. Generally, 900 MHz VCO frequency, and 0.5 MHz output frequency has been selected. The low output frequency helps to see any glitches and jitter on my rather moderate scope I am using here (a 60 MHz Tektronix analog scope). At each setting, I increased the reference frequency until the Si5351 lost phase lock. Also, I reduced the power level at each frequency until some jitter showed up in the output.
The tests took more setting than expected – because the Si5351 can handle a huge range of reference frequencies – well beyond the 25 to 27 MHz, and even the internal divider can be set outside of the specified range (necessary only for the highest reference clock frequencies). A particular useful fact – the Si5351A can accept input frequencies of 100 MHz easily – I have some microwave PLLs running of a 100 MHz (rather than 10 MHz) reference.
As you can see, the internal VCO is working from about 170 to about 1100 MHz, so the 600-900 MHz is a good suggestion, but you can also run the VCO at, say, 500 or 550 MHz, if needed in some specific case of division factors (it is always much better to use integer-only divisors, rather than any fractional terms which introduce jitter and spurious signals.
After all this study, we can also plot the input sensitivity (signal from a 50 Ohm source, directly AC coupled to the XTAL A input, XTAL B floating, no other termination – probably, I will measure the characteristic impedance of the input later, no suitable test equipment currently available here in my temporary Japanese workshop).
As you can, see there is no tuned circuit or anything like it, the xtal input can accept any signal up to the highest relevant frequencies, and at lower frequencies, you just have to drive it a bit harder. 10 MHz may be the useful low limit (I suggest you drive it at 3-5 dBm when using 10 MHz, which will be about 6 dB above the sensitivity threshold).
Now, up for some long term test in the actual GPSDO application!