Reference Signal Conditioning: 10 MHz amplifier/limiter, :2 divider, 5 MHz output

A common task for most projects involving a PLL or other RF circuitry requiring a reference frequency signal is the conditioning of the incoming reference. These reference signals are typically very accurate in frequency, but never very accurate in levels, nor at the levels constant (sometimes, multiple instruments are connected to a single 10 MHz source, an disconnected when the setup is re-configured etc.). Also, there is always a risk of incorrect connection, with all these BNC inputs.

Therefore, we have a few requirements:

(1) Input needs to be stable to a reasonable DC voltage, say, a few Volts.

(2) Input needs to widthstand at at least 20-25 dBm input, about 0.25 Watts.

(3) Input needs to widthstand ESD, or other transients, and provide reasonable termination to avoid reflection. In the given case, we want about 50 Ohm – some reference inputs have higher resistance.

(4) Circuit needs to work from about -10 dBm on, up to 10 or 20 dBm, with no significant change in jitter, etc., and provide a stable, constant level output, TTL levels, or whatever is required.

The current circuit, which is intended to be a reference signal conditioner for a Micro-Tel MSR-904A Microwave Receiver, also needs a 5 MHz output – the PLL will run off 10 MHz, but the MSR-904A still is ancient enough to require 5 MHz (5 MHz used to be the standard reference frequency from early times up until the end of the 70s – since then, 10 MHz is almost exclusively used, and sometimes, 100 MHz, for double-digit GHz circuits).
Such 5 MHz output is easily realized by a divider circuit, based on a 74F74.

Now, how do we achieve all this. Well, here is the schematic:
ref signal conditioner schematic

The essential part – a 74HCU04. This little circuit is extremely useful – get a handful of these, they are not just “inverters” but acutally work at frequencies from DC to many MHz, can source and sink at least 4 mA to 5 V. The 74HCU04 is more or less a set of 6 push-pull MOSFET pairs, in a handy package. These pairs can also be paralleled with no precautions to get more current, if needed.

The signal input is protected by a 56 Ohm termination (which can burn out if you feed excess DC or more than 0.25 W of RF – unlikely to happen). Then, there is a 47 n decoupling capacitor, a series resistor, and a clipping circuit – which will most likely never be activated.
The 22k resistor, along with the first inverter, and the 470 Ohm resistor form the first amplifier.

Signal A (see letter on schematic, input of first inverter):
ref signal circuit A
-scope is set to 1 V per div vertical, 50 ns per div horizontal.

Output B:
ref signal circuit B

Note that the first gate is self-biased, no need to adjust anything.

This is then squared-up by the limiting action of the following 2 inverters:
ref signal circuit C

ref signal circuit 10 mhz E 1 v-div 50 ns-div

Now, we have a clean 10 MHz square wave. This is fed to a 74F74 edge-triggered flip-flop. The 74F74 is pretty fast, it easily works up to 100 MHz and will provide fast-rising edges.
The flip-flop will also ensure pretty much exact 50% duty cycle of the 5 MHz output.

ref signal circuit 5 MHz F

The output is fed through a low pass, 51 Ohm – 470 p, about 6.6 MHz, because we want low jitter at the divider stage (fast rise time pulses feeding the flip-flop), but not too steep edges at the output:
ref signal circuit G

After amplification by another 74HCU04 inverter:
ref signal circuit 5 MHz H
– this signal is still referenced to ground, and after another resistor and capacitor, finally, an AC signal, that can be used for various purposes, including frequency locking a MSR-904A.
ref signal circuit 5 mhz output I

Note: when you measure in such circuits, always use a >10 Meg, 10:1 low capacitance probe. Otherwise, you will get results, but these won’t reflect reality.

A quick test with a 10 MHz test signal – the circuit works well from about -22 dBm to 20 dBm, no issues at all. For the specification, and to ensure that is is working even under awkward conditions, we might limit it to -10 dBm to +16 dBm.

The little thing in action:
ref signal circuit test setup

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