HP 8970A Noise Figure Meter: A7 voltmeter assy fix

Finally, some capacitors arrived, Panasonic ECW FD type, polypropylene dielectric. These are very much suitable for any type of active filter or sample/hold circuits, thanks to their good capacitance stability, and low dielectric absorption.

8970a a7 assy cap replacement ecw-fd2w154jq

8970a ecwfd capacitor data

Dielectric adsorption, not something specified on the datasheet. So I did a quick test, using a 50 Volt power supply, a 100 Ohms resistor, and a high-impendance (10 GOhm or more) voltmeter. Test follows this sequence:
(1) Charge capacitor for about 10 minutes; make sure to limit charge current to a few 10s of mA.
(2) Discharge for 10 seconds, using a 100 Ohm resistor.
(3) Measure voltage and record maximum value (V_measured) – typically, this takes several seconds.
(4) Calculate: V_measured/50 Volt *100%, the number obtained is a measure of dielectric absorption, in %.

Results: 0.005% for the ECW FD (Panasonic brand, PP dielectric), and 0.09% for the original cap, HEW-446 series (TRW brand, PET dielectric). Not bad, rule of thumb says that PP has 5x lower absorption than PET, well, but don’t quote me on the numbers measured – these are just rough estimates, fair enough. Needless to say, the new capacitors will outperform the original ones by far – and hopefully last as long, or longer, 30+ years….

Another detail. Note the line on the top side of the A7 board, close to one terminal of the capacitor? This is the outer winding of the capacitive layer. This goes to ground. The ECW FD aren’t marked for their winding direction (these are non-polar caps, but still, there is an outer layer of foil, and an inner layer, and the outer layer does pick up more noise, and thus needs to go to the lower impedance connection). But the winding direction can easily be determined, just connect the capacitor to an oscilloscope probe, and hold the part between your fingers – then, swap the probe (switch ground and hot connection). You will see different levels of noise on the screen, mainly, 50/60 Hz hum. Select the connections for lowest noise, and the ground lead of the oscilloscope probe will then indicate the outer layer of the winding. Best, mark it with a felt pen.

8970a a7 assy caps replaced

USB RTL SDR 28.8 MHz Reference: dividers, PLL, success

With the 28.8 MHz VCO design established, all we need to move this project on are divers for the 28.8 MHz (VCO) and 10 MHz (Reference) signals, a slow-acting PLL, and some auxilliary circuitry to feed the 28.8 MHz back to the RTL SDR.

The 28.8 MHz and 10 MHz signals are AC coupled with about 1 kHz input impedance, this is quite common for any 10 MHz reference signal input (used for various kinds of test equipment). These signals are then amplified/limited by unbuffered inverters, 74HCU04. This is a very cost-effective and easy solution, the HCU04 has push-pull outputs, and input clamping diodes. Still, some clamp diodes have been added for the 10 MHz input, just in case.

28.8 mhz divider chain schematic

Looking at 28800 kHz, and 10000 kHz, 400 kHz is the largest common denominator. Accordingly, we need :72, and :25 division factors.

Division of the 10 MHz down to 400 kHz is accomplished by two 74LS90, but you can use other TTL decade dividers, these were just the circuits I had in stock.
28.8 to 400, a bit more tricky, first, divided by 8, using a 74LS293, and another LS293 that has two diodes, acting as an “OR”, to reset the counter when count 9 is reached.

Both 400 kHz signals are then compared use a flip-flop phase comparator, conveniently packaged in a 4046 PLL. For convenience, and to avoid digital noise on the 12 V rail powering the VCO, the 4046 is powered only from 5 V. This somehow limits the tuning output range, from close to 0 V, to about 3.1 V.

The loop filter is very slow acting, tens of seconds, because the objective of this PLL is to correct long-term drift of the 28.8 MHz reference, introduced by temperature, Xtal drift, etc., but otherwise not to impact its noise and oscillation characteristics.

28.8 mhz pll and loop filter schematic

The VCO (see earlier post, VCO design) uses a fixed capacitor to set the tuning offset, this was changed to 4.4 pF, and finally to 2.2 pF, to properly center the tuning voltage (V_tune, output of the PLL loop filter buffer) within the 4046 output range, at roughly 1.7 V.
Extentensive testing was carried out the ensure that the VCO starts up properly, even if extreme V_tune voltages are applied; as the 28.8 MHz Xtals used in the USB RTL SDR devices may vary, you will need to check the required tuning range and pullability of the Xtal. Some Xtals oscillators will stop oscillating, if you pull to frequency up or down too much, which might happen during PLL start-up. This can lead to an undesirable lock-up condition.

Here are the tuning characteristics, for 2p2, and 4p4 pF VCO capacitor values.

28.8 mhz tuning

This is the divider and PLL board. Sure it would be much nicer to have everything completely separated, in shielded cans, etc., but I did not go to such effort. Later testing will reveal if it has any bad consequences for the 28.8 MHz phase noise, but so far, I don’t see much noise – will do a more in-depth comparison later.

28.8 mhz pll boad